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vaclav
Visitor
Visitor
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Registered: ‎02-20-2014

PAR max frequency report - with unregistered and registered inputs

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Hello,

I have a design and I get completely different max frequency from PAR Report if I put the inputs registered and if not. Why is that?

For unregistered inputs I got 309 MHz and for registered inputs I got 211 MHz. This way, one can't say it's because of the input routing, because then the registered inputs version should be faster, but it's not.

 

My design is like this:

 

          ---- Combinational logic ---- 

Input ---- Combinational logic ---- Mux select  ---- Output register

Input ---- Combinational logic ----

          ---- Combinational logic ---- 

 

With input registers:

 

                                 ---- Combinational logic ---- 

Input ---- Register ---- Combinational logic ---- Mux select  ---- Output register

Input ---- Register ---- Combinational logic ----

                                 ---- Combinational logic ---- 

 

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driesd
Xilinx Employee
Xilinx Employee
15,911 Views
Registered: ‎11-28-2007

Hi Vaclav,

 

this is expected behaviour: when you use registered inputs, the tool is forced to place the registers that drive the I/O pads directly in the IO-pads. This is beneficial for your I/O timing, but it means longer delays between these I/O register and the logic driving the I/O registers.

 

Otherwise, without registered inputs, all logic can be placed close together in fabric.

 

If you want to increase your maximum frequency and you can take additional latency on these signals, I would recommend to add pipeline registers.

 

 

Best regards,

Dries

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driesd
Xilinx Employee
Xilinx Employee
15,912 Views
Registered: ‎11-28-2007

Hi Vaclav,

 

this is expected behaviour: when you use registered inputs, the tool is forced to place the registers that drive the I/O pads directly in the IO-pads. This is beneficial for your I/O timing, but it means longer delays between these I/O register and the logic driving the I/O registers.

 

Otherwise, without registered inputs, all logic can be placed close together in fabric.

 

If you want to increase your maximum frequency and you can take additional latency on these signals, I would recommend to add pipeline registers.

 

 

Best regards,

Dries

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gszakacs
Professor
Professor
9,397 Views
Registered: ‎08-14-2007

Dries,

 

  I don't think this is a case of packing into IOB.  In the first diagram there is only one register in the path through the FPGA.  In that case the only thing that affects the PERIOD constraint is the component switching limit.  All timing of interest in the design would be covered by OFFSET IN and OFFSET OUT constraints.

 

In the second case, regardless of the register placements, you now have an internal path between two registers which govern the PERIOD constraint.  Again it would be expected that this reduces the max frequency.  Packing registers into the IOB's would reduce it even further.

-- Gabor
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