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Registered: ‎06-06-2018

PCI Express Timing issues. Timing Failed

Hello everybody!!
I use PCIe DMA core in my project with parameter: x4 lane, 5GT/s reference clock 100mhz, axi clock 250mhz with bus 64bit and Vivado ver. 2018.1.

Target xc7a100tfgg484-2

Project are working, data is transmitted through the PCI without problems but I have a timing problems with inner clocks: clk_125mhz_mux_x0y0, clk_250mhz_mux_x0y0, userclk1 and others.

Screenshot_mypci.png

I don't understend what do I need to do to solve problems. Can constraint this clocks or I need to set parameters?

Perhaps tell me where to find information in the ip documentation.

PS: I attached PCIe xci file

 

Thank you for your help.

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1 Reply
Scholar markcurry
Scholar
283 Views
Registered: ‎09-16-2009

Re: PCI Express Timing issues. Timing Failed

(EDIT this is the timing forums.  Sigh - my reading comprehension isn't awake yet this morning...)

The fact that their are HOLD time problems implies clock setup problems - but I can't tell from the details you've given.

I'd suggest providing a bit more detail on the clocking setup - and consider asking the mods to move this post to the timing forum.

Regards,

Mark