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Adventurer
Adventurer
422 Views
Registered: ‎08-01-2017

PLL/MMCM gated clock input

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I am using KCU105 Evalution Board.

I have a gaped clock that is output of a BUFGCE. I want to use it as the input of PLL/MMCM and config the PLL/MMCM to 1:1 output (output has the same frequency as input).

Output of BUFGCE is like the original input of it with few clock pulses removed from it. For example as in the instance below, clk_line is 100MHz and clock enable of BUFGCE is 99time '1' and 1time '0'. Thus creating 99 clock pulses at the clk_gated output out of 100 clk_line pulses.

Now my question is if I connect the clk_gated to the input of mentioned PLL/MMCM what will happen? Would it remove the jitter and make a clean and periodic 99MHz clock at output?

 

BUFGCE_inst : BUFGCE
port map(
O => clk_gated, 
CE => clk_ctrl, 
I => clk_line 
);

 

Thanks in advance.

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1 Solution

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Historian
Historian
303 Views
Registered: ‎01-23-2009

Re: PLL/MMCM gated clock input

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As @drjohnsmith said, the internal PLL/MMCM in the FPGA cannot do this. This clearly violates the MMCM_Finjitter (or PLL_Finjitter, which is the same), of 1ns or 20% of Fin MAX (see DS892 tables 36 and 37). You are attempting to deal with a jitter that is 100% of the Fin (one full clock period) - clearly more than the MMCM/PLL can tolerate. If you do this the MMCM/PLL will almost certainly just lose lock.

Avrum

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7 Replies
Mentor hgleamon1
Mentor
398 Views
Registered: ‎11-14-2011

Re: PLL/MMCM gated clock input

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What is the origin of the clk_line? If the MMCM is a 1:1 ratio, what is the purpose of putting it after the BUFGCE? I'd have to check but maybe the MMCM will lose lock if the input clock is not continuous.

How much logic will be clocked by the gated clock? It may be easier to simply create a clock enable to skip the single clock pulse every 100 pulses, rather than complicate the clock design.

If you decide you must have a MMCM, then put the BUFGCE after the MMCM and not before it.

----------
"That which we must learn to do, we learn by doing." - Aristotle
Highlighted
385 Views
Registered: ‎01-22-2015

Re: PLL/MMCM gated clock input

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@arashkm73 

I agree with @hgleamon1 that there must be a better way to do what you are trying to accomplish. Also, the MMCM and PLL have a minimum clock-input duty cycle specification of about 30% - see the datasheet for your device.

Mark

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Adventurer
Adventurer
379 Views
Registered: ‎08-01-2017

Re: PLL/MMCM gated clock input

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thanks for your reply.

 

It is the output of an MMCM.

The target is to adjust the output frequency with some logic algorithm. This is done through clock enable of BUFGCE. And I also want the output clock cleared and distributed (Continuous).

So I read somewhere I should use a Low Pass Filter or PLL and connect the gated clock to it. This is why i am setting MMCM to 1:1 ratio. To see if it could give me a monotonic clock.

 

about 5k LUT and 6k FF

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Adventurer
Adventurer
375 Views
Registered: ‎08-01-2017

Re: PLL/MMCM gated clock input

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Also, the MMCM and PLL have a minimum input duty cycle specification of about 30% - see the datasheet for your device.

 


Is this constraint on duty cycle only? I mean MMCM/PLL is facing a clock with correct duty cycle, but there are some missing clocks in it.

According to your answer, is the missing clock treated as a 0% duty cycle ?

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Scholar drjohnsmith
Scholar
326 Views
Registered: ‎07-09-2009

Re: PLL/MMCM gated clock input

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Sounds like you are after keeping a clock running when the input clock stops,

The PLL / MMCM in the FPGA is not designed for this sort of thing,

External / BIG phase locked loops can have their loop filter tuned to keep the output frequency constant for a longer time than the FPGA,

Using the internal PLL/ MMCM is not the way forward.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Historian
Historian
304 Views
Registered: ‎01-23-2009

Re: PLL/MMCM gated clock input

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As @drjohnsmith said, the internal PLL/MMCM in the FPGA cannot do this. This clearly violates the MMCM_Finjitter (or PLL_Finjitter, which is the same), of 1ns or 20% of Fin MAX (see DS892 tables 36 and 37). You are attempting to deal with a jitter that is 100% of the Fin (one full clock period) - clearly more than the MMCM/PLL can tolerate. If you do this the MMCM/PLL will almost certainly just lose lock.

Avrum

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Adventurer
Adventurer
262 Views
Registered: ‎08-01-2017

Re: PLL/MMCM gated clock input

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Many thanks for everyone's helpful replies.

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