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Explorer
Explorer
124 Views
Registered: ‎09-08-2009

PLL lock signal timing

 

How long does it take the lock output of a PLL to respond, when the input clock is missing.

This information cannot be found on the datasheet of the 7 series.

 

 

2 Replies
Participant evant_nq
Participant
85 Views
Registered: ‎07-18-2018

Re: PLL lock signal timing

hi 999068709169,

    i tried looking this up, if it's in any of the 7 series documentation, it's not obvious.

You are asking how many ns it takes for the lock to de-assert after the input clock stops?

I might think that if you look at the get_speed_models, of the arc through the MMCM for the lock pin, that value might reflect a reasonable estimate of the time from the clock input to the locked that you could expect, but that's just a guess.

 

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45 Views
Registered: ‎01-22-2015

Re: PLL lock signal timing

@999068709169

As evant_nq says, its not obvious from the documention.

However, I find on page 83 of UG472 for MMCM/PLL that, “LOCKED will be deasserted within one PFD clock cycle if the input clock stops..”.

From Kintex-7 datasheet (DS182, page 47), the minimum frequency, PLL_FPFDMIN, of the Phase Frequency Detector (PFD) is 19MHz.  So, LOCKED should be deasserted within 1/19MHz=53ns after the input clock stops.

Cheers,
Mark

 

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