01-09-2019 06:52 AM
How long does it take the lock output of a PLL to respond, when the input clock is missing.
This information cannot be found on the datasheet of the 7 series.
01-11-2019 07:10 AM
i tried looking this up, if it's in any of the 7 series documentation, it's not obvious.
You are asking how many ns it takes for the lock to de-assert after the input clock stops?
I might think that if you look at the get_speed_models, of the arc through the MMCM for the lock pin, that value might reflect a reasonable estimate of the time from the clock input to the locked that you could expect, but that's just a guess.
01-12-2019 04:58 PM
As evant_nq says, its not obvious from the documention.
However, I find on page 83 of UG472 for MMCM/PLL that, “LOCKED will be deasserted within one PFD clock cycle if the input clock stops..”.
From Kintex-7 datasheet (DS182, page 47), the minimum frequency, PLL_FPFDMIN, of the Phase Frequency Detector (PFD) is 19MHz. So, LOCKED should be deasserted within 1/19MHz=53ns after the input clock stops.