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Newbie ch@ndu213
Registered: ‎10-22-2018

Physical design

What may the reason for hold violations even though i have no violations in postcts opt stage?

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2 Replies
Registered: ‎07-18-2018

Re: Physical design

What are the steps you are doing to run the design? What stage of the design says it has no hold errors, and which stage of the design says it does have hold errors?

Can you write out checkpoints for both, and then open them and check if the hold error is in just one of the DCPs?

Once you've done that, from the design with the failing hold errors, get the path details from the report_timing_summary

Copy the full path of the FROM and TO locations including the pin name

Then create this command:

report_timing -from [get_pins <Insert that full FROM path>] -to [get_pins <Insert that full TO path>] -nworst 1 -max_paths 1 -name <Working/Notworking_rpt>

This will open just that path up in the failing checkpoint. Confirm it does. Now you can open the checkpoint that is passing, and call the exact same tcl command. You should be able to see what it thinks is different between the two paths.

And you can post the paths, and which steps in implementation the difference is appearing in.

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Registered: ‎01-22-2015

Re: Physical design


As evant_nq says, we need more information about the problem you are seeing.

Vivado is usually very good at getting rid of hold-time problems.

Here are some design mistakes that often lead to hold-time problems:

  1. Routing a clock out of the clock-tree (ie. through the FPGA fabric)
  2. Writing a constraint on a FPGA clock input when IP (eg. Clocking Wizard) has automatically written the constraint for you.
  3. Using BUFGMUX without writing the proper “logically exclusive clock groups” constraints.
  4. FPGA IO (ie. FPGA communication with an external device) that has not been designed or constrained properly


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