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shaikon
Voyager
Voyager
348 Views
Registered: ‎04-12-2012

Position on the "edge" switch in timing constraints

Hello,

Are the the following 3 constraints 100% equivalent ?

set_input_delay -min -0.8 -clock_fall -clock [get_clocks some_clock] [get_ports {some_port}]
set_input_delay -min -0.8 -fall -clock [get_clocks some_clock] [get_ports {some_port}]
set_input_delay -min -0.8 -clock [get_clocks some_clock] [get_ports {some_port}] -clock_fall

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klumsde
Moderator
Moderator
337 Views
Registered: ‎04-18-2011

Arguments:

-clock <arg> - (Optional) Indicates that the input delay is relative to the
specified clock. By default the rising edge is used. However the
-clock_fall argument can be used to indicate that the falling edge should
be used instead.

-reference_pin <arg> - (Optional) Specifies that the delay is relative to
the active edge of a clock appearing on the specified pin or port rather
than a clock.

-clock_fall - (Optional) Specifies that the delay is relative to a falling
edge of the clock rather than rising edge.

-rise - (Optional) Specifies the input delay applies to rising transitions
on the specified ports. The default is to apply the delay for both rising
and falling transitions.

-fall - (Optional) Specifies the input delay applied to falling transitions
on the specified ports. The default is to apply the delay for both rising
and falling transitions.

 

I expect the first and the 3rd constraint are the same. the problem with the 2nd one is that it is using the -fall option which seems to say that the input delay is only valid for falling transitions on the signal...

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shaikon
Voyager
Voyager
308 Views
Registered: ‎04-12-2012

This is what avrum had to say about the subject:

https://forums.xilinx.com/t5/Timing-Analysis/Timing-Analysis-about-input-delay/td-p/786262

search for the string "we do not select the check" in the link.

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