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sttrue80
Visitor
Visitor
6,197 Views
Registered: ‎02-18-2010

Post-Route Simulation

Hi friends,

 

I am new in this technology. Recently I wrote a program by VHDL whcih I don't have any problem in behavioral simulation and evrything is fine and the circuit output is as expected. but in post-route simulation,the output which is a 64 bit vector is set to X value.

 

Can you please give me some guidlines and maybe manuals to tell me what should i concern when i want to simulate in post-route section? actually i want to know what factors affect on post-route simulation rather than behavioral one?

 

Thanks.

 

sttrue80

 

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hobson
Xilinx Employee
Xilinx Employee
6,153 Views
Registered: ‎04-15-2008

Hi sttrue80,

 

As you probably know, post-route simulation is a gate level simulation in which (by default) worst-case timing values are applied to every element in the design.  What may have worked in behavioral simulation (ideal case) may not work in timing simulation.

 

My first suggestion is to remove the file containing the timing delays (often the SDF file) from the post-route simulation.  In effect, you will be performing a post-route, gate level  simulation without any timing information.  If the simulation begins to behave correctly, then you know the problem is purely a timing issue.  If it produces incorrect results, then you first need to go off and figure out the functional issue.

 

Once you've got any functional issues resolved, resimulate the design with the timing delay file added back in.  If you're still getting X's, then you know it's purely a timing issue.

 

Now, the most likely reason you're seeing X's in your simulation is that your design doesn't meet the timing constraints you've applied, or the set of timing constraints isn't complete.

 

You probably need to make sure your design really achieved the timing constraints you applied.  Double check the PAR and TWR reports to confirm.  Next, generate an unconstrained paths report and determine whether anything got missed.  Many times unconstrained paths really are "don't cares," but you should make sure the paths you intend to constrain are really being constrained.

 

If your static timing analyses look good, then go back to your timing simulation and trace the X's upstream from your 64-bit vector.  X's generally get propagated from upstream logic, so you have to figure out the true source of the X's.  Hopefully that will also give you a clue as to why they're being generated.

 

Regards,

-Hobson 

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bassman59
Historian
Historian
6,113 Views
Registered: ‎02-25-2008


sttrue80 wrote:

Hi friends,

 

I am new in this technology. Recently I wrote a program by VHDL whcih I don't have any problem in behavioral simulation and evrything is fine and the circuit output is as expected. but in post-route simulation,the output which is a 64 bit vector is set to X value.

 

Can you please give me some guidlines and maybe manuals to tell me what should i concern when i want to simulate in post-route section? actually i want to know what factors affect on post-route simulation rather than behavioral one?

 

Thanks.

 

sttrue80

 


The 'X'es are usually the result of an input synchronizer that does not meet set-up or hold times. As you should know, if you do not meet a flip-flop's set-up and hold times, the output can be metastable -- essentially unknown. Hence, this is modeled by an 'X' output.

 

Of course the 'X' is propagated through all of the logic -- any operation which has an unknown as an input has an unknown for an output.

 

In a functional simulation, the set-up and hold times are not ignored but are infinitesmal, so in essence you can ignore them. When doing a post-route simulation that uses real timing information, the set-up and hold times must not be ignored.

Message Edited by bassman59 on 03-25-2010 09:58 AM
----------------------------Yes, I do this for a living.
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