01-12-2019 07:43 PM
Every time I try to run post-implementation timing simulation, I get the posted error message in my Tcl console one to two hours into the elaborate step. As far as I can tell, there is no error file created. The elaborate.log file seems pretty normal:
Vivado Simulator 2018.2 Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. Running: /home/mapsa/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto 203b8338afda4ca698fc11a22157fa48 --incr --debug typical --relax --mt off --maxdelay -L xil_defaultlib -L simprims_ver -L sec ureip --snapshot tracklet_L2_tb_time_impl -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.tracklet_L2_tb xil_defaultlib.glbl -log elaborate.log Turned off multi-threading. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis
Any ideas on what could be causing this issue?
01-13-2019 05:52 AM
01-14-2019 08:56 AM
I tried this and got the same error (but with different number right before 'Killed'). The error also occurred after only about half an hour this time.
01-21-2019 11:03 AM
It appears that the reason for the crash was that my machine ran out of memory (18 GB). How much memory is normally needed to run the post-implementation timing simulation for ultrascale+ chips? (The part number for the chip I'm using is xcvu9p-flga2104-2L-e).
01-21-2019 04:12 PM
Thanks for reporting it back,
The memory recommendation for XCVU9P devices is as follows:-
Typical : 20 GB,
Peak : 32 GB.
Xilinx recommends to have at minimum enough physical system memory to handle the peak memory usage. (Please refer to Memory Recommendations for more information)
01-25-2019 01:50 PM
I added more memory to my machine, up to 32 GiB (the maximum my machine can house), and even this was not enough. The elaborate step still crashed on the same line after using up all 32 GiB. Is there anything I can do to reduce the memory usage of the simulation (besides cutting down the size of the design)?
01-27-2019 05:56 AM
Can you try running timing simulation in a example design given in Vivado and check if there also you are getting the same error, in that way we can confirm if the issue is design specific or machine specific. Also, once try running your design in Vivado 2018.3. Please let me know if it passes there.
01-28-2019 03:22 PM
I was able to get the simulation working when I cut down the size of my design (I had a generate loop creating 5 copies of a large module and I reduced this to just 1). So I think the issue was design specific. I will try simulating the full design in Vivado 2018.3 and report back.
01-29-2019 03:48 PM
The same crash occurred in Vivado 2018.3-- the elaborate step used up all of the available memory and then crashed.