UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor sw.mikolaj
Visitor
14,487 Views
Registered: ‎03-03-2009

Post place&route simulation of 3 inverter oscillator

Hi. I need to create oscillator inside of FPGA. It can't be external CLK because i've to design PLL. I Try to connect three inverters and i do it with usage of LUTs. After synthesis i've got such connection. Next i make implementation and I generate post-place & route simulation model. Everything is made without any errors. Then i go to "sources for : post route simulation" ( i use default ise simulator) and i find 1st error : i can't compile HDL simulation libraries and information says, that ise simulator isn't supported. I don't really know if such compilation is needed. But when i try to run simulation ( i choose file which is produced from generate post-place & route simulation mode and double click on simulate post-place and route model) it  looks like it goes fine, simulation starts but when i see results there is nothing in there. On every output i see only "x".  I attach my project code. I connect three luts and output of third inverter is connected to input of first inverter. I would expect that on plot i see oscillation with frequency depended on single inverter delay and path delay, but i see only "x".

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DCO is
    Port ( OUTA : out  STD_LOGIC;
           OUTB : out  STD_LOGIC;
           OUTC : out  STD_LOGIC);
end DCO;

architecture Behavioral of DCO is
signal a,b,c,d,e,f:std_logic;
        attribute keep : boolean;
        attribute keep of a,b,c:signal is true;
        attribute keep of OUTA,OUTB,OUTC: signal is true;
       
begin
-- LUT1: 1-input Look-Up Table with general output
-- Xilinx HDL Libraries Guide, version 10.1.2
        LUT1_inst : LUT2
        generic map (INIT => "01")
        port map (
        O => b, -- LUT general output
        I0 => a, -- LUT input
        I1 => d
        );
        -- End of LUT1_inst instantiation
        LUT1_inst1 : LUT2
        generic map (INIT => "01")
        port map (
        O => c, -- LUT general output
        I0 => b, -- LUT input
        I1 => e
        );
        -- End of LUT1_inst instantiation
        LUT1_inst2 : LUT2
        generic map (INIT => "01")
        port map (
        O => a, -- LUT general output
        I0 => c, -- LUT input
        I1 => f
        );
        -- End of LUT1_inst instantiation   
       
OUTA<=a;
OUTB<=b;
OUTC<=c;   
d<= (a and (not b));

end Behavioral;
 

 

0 Kudos
8 Replies
Historian
Historian
14,481 Views
Registered: ‎02-25-2008

Re: Post place&route simulation of 3 inverter oscillator


sw.mikolaj wrote:

Hi. I need to create oscillator inside of FPGA.
 

 


 

good luck with that ...

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Visitor sw.mikolaj
Visitor
14,464 Views
Registered: ‎03-03-2009

Re: Post place&route simulation of 3 inverter oscillator

Why good luck ? I know that if I do implantation of that project there would be oscillator, cause 3 inverters are always oscillating. What did u mean by " -a " is this some option ? Where should i put it ?
0 Kudos
Historian
Historian
14,446 Views
Registered: ‎02-25-2008

Re: Post place&route simulation of 3 inverter oscillator


sw.mikolaj wrote:
Why good luck ? I know that if I do implantation of that project there would be oscillator, cause 3 inverters are always oscillating. What did u mean by " -a " is this some option ? Where should i put it ?

Oy.

 

There's no reasonable way to control an oscillator built out of a ring of inverters in an FPGA. Serious users will recommend against even trying it. It is a fool's errand.

 

The "-a" is simply a signature -- my first name starts with A.

 

What do you mean by "u"? Is that some kind of code?

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Visitor sw.mikolaj
Visitor
14,437 Views
Registered: ‎03-03-2009

Re: Post place&route simulation of 3 inverter oscillator

Sorry, "U" was only a shortcut from You , no offence :)

I know that inverter is not a good device for oscillator, but without external elements that is only way to do it inside FPGA.

And about control :

I thought that i could make a chain of inverters which make a chain of delay elements and getting signal after some count of elements brings me overall delay which decides about frequency. The problem is that in real IC that delay depends on voltage, temperature and process so there is no way to be sure what is exact delay of particular inverter. Are there available models that brings information about delays in diffrent corners ? Like delay in 10% lower voltage then nominal, higher temperature so i could simulate delays in diffrent conditions just to make sure that oscillator operates properly in diffrent conditions? 

Message Edited by sw.mikolaj on 03-04-2009 12:39 PM
0 Kudos
Xilinx Employee
Xilinx Employee
14,416 Views
Registered: ‎08-13-2007

Re: Post place&route simulation of 3 inverter oscillator

It is possible to build a LUT-based ring oscillator.

Is it recommended - absolutely not... Nearly all applications should use an external oscillator input.

 

Some helpful information here (for academic study - not to encourage you):

http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
 http://www.xilinx.com/products/boards/s3estarter/files/s3esk_frequency_counter.pdf (page 9)
 http://www.xilinx.com/products/boards/s3estarter/files/s3esk_frequency_counter.zip (ring_osc.vhd)

There are several possible issues:

-optimization by back-end tools (addressed above)

-wide possible variation based on PVT. Even worse if you don't control placement and routing (via DIRT strings, e.g. directed routing)

-determining min and max associated frequency

I also imagine most simulators would have issues here too because of the combinatorial feedback loop.

 

Proceed at your own risk.

 

bt

0 Kudos
Visitor sw.mikolaj
Visitor
14,410 Views
Registered: ‎03-03-2009

Re: Post place&route simulation of 3 inverter oscillator

Hi. I've builded it with LUTs and placed them with RLOC atribute, but i find that is is completely useless. It's impossible to control that oscillator, cause between two neigbouring frequencies is 100MHz diffrence, so i pass this conception. Thnak you all very much for Your replies :)
Tags (1)
0 Kudos
Highlighted
Visitor yueguoguo
Visitor
10,784 Views
Registered: ‎08-29-2012

Re: Post place&route simulation of 3 inverter oscillator

Hi mikolaj

 

I am designing a 3-stage oscillator now and going to study how the spatial impacts affect the frequency of the oscillators.

Now I am stuck at how to correctly put the oscillator design into a macro and place&route the macro into my top-level design.

Can you give me any detailed description about how you achieved this?

Or, maybe you have other strategies for a better outcome? : )

 

Thanks in advance.

 

-yueguoguo

Tags (1)
0 Kudos
Historian
Historian
10,744 Views
Registered: ‎02-25-2008

Re: Post place&route simulation of 3 inverter oscillator


@yueguoguo wrote:

Hi mikolaj

 

I am designing a 3-stage oscillator now and going to study how the spatial impacts affect the frequency of the oscillators.

Now I am stuck at how to correctly put the oscillator design into a macro and place&route the macro into my top-level design.

Can you give me any detailed description about how you achieved this?

Or, maybe you have other strategies for a better outcome? : )

 

Thanks in advance.

 

-yueguoguo


The gist of this (ancient) thread is : don't bother.

----------------------------Yes, I do this for a living.
0 Kudos