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simozz
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Registered: ‎05-14-2017

Post synthesis and Implementation simulations with AXI VIP

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Hello,

I have a small block-design (which includes 2 AXI4-Lite VIP packages) that I use to simulate a custom core which seems to work fine.

Now I want to run a post-synthesis and post-implementation simulations, both functional and timing, but xsim returns the error

ERROR: [VRFC 10-2989] 'design_2_axi_vip_0_0_pkg' is not declared [/path/to/project_5_4_2/project_5_4_2.srcs/sim_1/new/design_2_tb.sv:23]

What's wrong with AXI VIP Packages ?

Could someone suggest a tutorial or a guide to run post synthesis and Implementation simulations ?

Thanks.

s.

PS: in my projects there are 2 block-designs: the design_1 final one for which I build the bit stream, and design_2. This last one is used for simulation.

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simozz
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Scholar
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Registered: ‎05-14-2017

Reading the appropriate docs I learnt that AXI VIP cannot be used for these purposes.

Behavioural simulation only.

s.

View solution in original post

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simozz
Scholar
Scholar
163 Views
Registered: ‎05-14-2017

Reading the appropriate docs I learnt that AXI VIP cannot be used for these purposes.

Behavioural simulation only.

s.

View solution in original post

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