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bell_a
Visitor
Visitor
2,718 Views
Registered: ‎01-30-2018

Problem with fifo_clocks.xdc

Hello!
I'm doing a project using IP. When implementing, I have the following:
Warnings: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_ports -scoped_to_current_instance wr_clk]'. ["e: /project/modulator/modulator.srcs/sources_1/ip/fifo/fifo/fifo_clocks.xdc": 53]
Critical Warning: [Common 17-55] 'get_property' expects at least one object. ["e: /project/modulator/modulator.srcs/sources_1/ip/fifo/fifo/fifo_clocks.xdc": 55]

Fillet fifo_clocks.xdc:
set wr_clock [get_clocks -of_objects [get_ports wr_clk]]
set rd_clock [get_clocks -of_objects [get_ports rd_clk]]
set wr_clk_period [get_property PERIOD $ wr_clock]
set rd_clk_period [get_property PERIOD $ rd_clock]
set skew_value [expr {(($ wr_clk_period <$ rd_clk_period)? $ wr_clk_period: $ rd_clk_period)}]

# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
set_false_path -from [filter [all_fanout -from [get_ports wr_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME = ~ * gdm.dm_gen.dm * / gpr1.dout_i_reg *}]


# Set max delay on cross-clock domain path for Block / Distributed RAM based FIFO

set_max_delay -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * rd_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .wr_stg_inst / Q_reg_reg [*]] -datapath_only [get_property -min PERIOD $ rd_clock]
set_bus_skew -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * rd_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .wr_stg_inst / Q_reg_reg [*]] $ skew_value

set_max_delay -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * wr_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .rd_stg_inst / Q_reg_reg [*]] -datapath_only [get_property -min PERIOD $ wr_clock]
set_bus_skew -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * wr_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .rd_stg_inst / Q_reg_reg [*]] $ skew_value

I do not understand what I'm doing wrong, please help.

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8 Replies
vemulad
Xilinx Employee
Xilinx Employee
2,710 Views
Registered: ‎09-20-2012

Hi @bell_a

 

You should create clock constraints for FIFO clocks in your top level XDC, refer to this AR for more details https://www.xilinx.com/support/answers/66666.html

Thanks,
Deepika.
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bell_a
Visitor
Visitor
2,663 Views
Registered: ‎01-30-2018

Can you tell me more? I must first set the time parameters in the xds file, right? And if it's already done? A large nesting in the project can cause such a problem?

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vemulad
Xilinx Employee
Xilinx Employee
2,648 Views
Registered: ‎09-20-2012

Hi @bell_a

 

Yes, you have define clock period constraints (create_clock) on the ports driving wr_clk and rd_clk inputs of FIFO generator IP in top level xdc. 

 

Nesting should not be a problem.

Thanks,
Deepika.
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bell_a
Visitor
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Registered: ‎01-30-2018

Ok. In the top xdc file, I create a clock that clock the entire circuit:
create_clock -period 10.000 -name RD_CLK -waveform {0.000 5.000} [get_ports RD_CLK]
create_clock -period 10.000 -name WR_CLK -waveform {0.000 5.000} [get_ports WR_CLK]
IP-core is used in the module, which is declared in the top module.

What should I change in fifo_clocks.xdc:
set wr_clock [get_clocks -of_objects [get_ports wr_clk]]
set rd_clock [get_clocks -of_objects [get_ports rd_clk]]
set wr_clk_period [get_property PERIOD $ wr_clock]
set rd_clk_period [get_property PERIOD $ rd_clock]
set skew_value [expr {(($ wr_clk_period <$ rd_clk_period)? $ wr_clk_period: $ rd_clk_period)}]

# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
set_false_path -from [filter [all_fanout -from [get_ports wr_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME = ~ * gdm.dm_gen.dm * / gpr1.dout_i_reg *}]


# Set max delay on cross-clock domain path for Block / Distributed RAM based FIFO

set_max_delay -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * rd_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .wr_stg_inst / Q_reg_reg [*]] -datapath_only [get_property -min PERIOD $ rd_clock]
set_bus_skew -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * rd_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .wr_stg_inst / Q_reg_reg [*]] $ skew_value

set_max_delay -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * wr_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .rd_stg_inst / Q_reg_reg [*]] -datapath_only [get_property -min PERIOD $ wr_clock]
set_bus_skew -from [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * wr_pntr_gc_reg [*]] -to [get_cells inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / * gsync_stage [ 1] .rd_stg_inst / Q_reg_reg [*]] $ skew_value

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thakurr
Moderator
Moderator
2,632 Views
Registered: ‎09-15-2016

Hi @bell_a

 

Since tcl is case sensitive, hence make sure you define the constraint for clocks in small letters:

create_clock -period 10.000 -name rd_clk -waveform {0.000 5.000} [get_ports rd_clk]
create_clock -period 10.000 -name wr_clk -waveform {0.000 5.000} [get_ports wr_clk]

 

Regards

Rohit

Regards
Rohit
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vemulad
Xilinx Employee
Xilinx Employee
2,626 Views
Registered: ‎09-20-2012

Hi @bell_a

 

Adding constraints in top level XDC should work, you need not touch IP XDC.

Thanks,
Deepika.
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bell_a
Visitor
Visitor
2,609 Views
Registered: ‎01-30-2018

Thanks. But with what then can my problem be connected?

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avrumw
Guide
Guide
2,583 Views
Registered: ‎01-23-2009

The constraint file for your FIFO is written as a "scoped" XDC file. This file is written in such a way so that it can constrain the FIFO inside the design in which it is being used.

 

As part of this, the FIFO constraints need to constrain the clock crossing paths. To do so, they need to know the periods of the write clock and the read clock. To do this, it queries the clock on the input ports of the module (WR_CLK and RD_CLK).

 

In your top design, it is your responsibility to

  a) connect the ports of the FIFO to clock nets and

  b) ensure that these clock nets are constrained (at the top level)

     - generally, this means placing a create_clock on all the clock inputs to your FPGA. If your FPGA is constructed correctly, this clock will propagate (either directly or through a generated clock through an MMCM/PLL) to the nets you have connected to the RD_CLK and WR_CLK ports of the FIFO

 

This error is telling you that it found no clock on the port of the WR_CLK or RD_CLK - so you have failed to correctly do one of the two things above.

 

Avrum

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