I'm design a fir filter for a project. It's divided as usual in data path and control path, with only one clock. Everything works fine.
In theory, the constraint i used for the ck is valid only for the data-path, while the rest can work with an higher frequency, and i have to check it. My idea was to create another ck (ck2); it's defined the same as the other clock and i changed the vhdl code putting ck2 instead of ck in the data-path processes.
Then i changed the constraints because i want ck with an higher frequency without any timing violation.
But even if the constraints are the same:
i have a timing violation in the inter-clock paths
I'm totally new with vivado and vhdl so any suggestion are welcome.