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Visitor
Visitor
2,612 Views
Registered: ‎07-03-2017

Problem with inter-clock paths

Hello,

 

I'm design a fir filter for a project. It's divided as usual in data path and control path, with only one clock. Everything works fine.

In theory, the constraint i used for the ck is valid only for the data-path, while the rest can work with an higher frequency, and i have to check it. My idea was to create another ck (ck2); it's defined the same as the  other clock and i changed the vhdl code putting ck2 instead of ck in the data-path processes.

 

ck vhdl.PNG

 

Then i changed the constraints because i want ck with an higher frequency without any timing violation. 

But even if the constraints are the same:

 

due ck.PNG

 

i have a timing violation in the inter-clock paths

 

error.PNG

 

error2.PNG

 

I'm totally new with vivado and vhdl so any suggestion are welcome. 

 

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Moderator
Moderator
2,567 Views
Registered: ‎11-09-2015

Re: Problem with inter-clock paths

HI @zackjoeee,

 

You should use a PLL/MMCM to generate new clocks (see the clocking wizard IP for easy instantiation).

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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