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Visitor volatile
Visitor
6,919 Views
Registered: ‎01-29-2009

Problem with the .ncd file

In EDK while generating the bit file, I got a timing constraint error which looks like this:

unning delay-based LUT packing...
ERROR:Pack:1653 - At least one timing constraint is impossible to meet because
   component delays alone exceed the constraint. A timing constraint summary
   below shows the failing constraints (preceded with an Asterisk (*)). Please
   use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
   PCF files to identify which constraints and paths are failing because of the
   component delays alone. If the failing path(s) is mapped to Xilinx components

 

Now I amtrying to analyse the system.ncd file using the timing analyser and seems there is some problem with the ncd file. This is the error that I get:

 

EXCEPTION:Pds:Pds_PahFileConv.c:50:1.20 - Corrupt Database.
ERROR:TimingToolsC:387 - A system error occured when trying to launch the
   process: trce /home/madhum/RA/edk_509/2_project/implementation/system_map.ncd
   /home/madhum/RA/edk_509/2_project/implementation/system.pcf -o
   /home/madhum/RA/edk_509/2_project/implementation/_ta_system_auto.twr -xml
   /home/madhum/RA/edk_509/2_project/implementation/_ta_system_auto.twx
Wind/U X-toolkit Error: wuDisplay: Can't open display

 

 

How can I debug the .ncd file? This error doesn't lead me to anywhere I think there is some problem with my ncd file only since when I run another project's ncd file it runs fine.

 

any feedback on this is much appreciable.

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2 Replies
Xilinx Employee
Xilinx Employee
6,787 Views
Registered: ‎07-30-2007

Re: Problem with the .ncd file

You can try to relax the constraints which will prevent the error and maybe allow you to get further.  You may also want to file a bug with a webcase for the database corruption.
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Xilinx Employee
Xilinx Employee
6,775 Views
Registered: ‎08-10-2008

Re: Problem with the .ncd file

I'm not sure if there's any relationship between those 2 errors, but the first error is always seen in failed global clock routing, especially when there's clock congestion in a clock region.
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