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Adventurer
Adventurer
310 Views
Registered: ‎08-15-2014

Pulse width timing violation even with the same CLOCK_DELAY_GROUP

hi,

for OSERDES3. I connect one  BUFG  for the output of MMCM, then connect to CLK port of oserdes.

BUFGCE_DIV to the output of MMCM, then connect to CLK_DIV of oserdes.

In the constraints, I add them to the same CLOCK_DELAY_GROUP.

set_property CLOCK_DELAY_GROUP MUX_and_BUFGCE [get_nets u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/clk_oserdes]
set_property CLOCK_DELAY_GROUP MUX_and_BUFGCE [get_nets u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/core_clk]

 

But I still see the pulse width timing violation if I improve the div_clk to 50Mhz and CLK(serial_clk) to 200Mhz. (clock ratio 1:4).

Why? How to solve this?

 

Pulse_width_timing.png
oserdes_clk_structure.png
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4 Replies
Historian
Historian
281 Views
Registered: ‎01-23-2009

Re: Pulse width timing violation even with the same CLOCK_DELAY_GROUP

Take a look at this post on the same problem - it appears that the CLOCK_DELAY_GROUP isn't sufficient.

Avrum

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Adventurer
Adventurer
262 Views
Registered: ‎08-15-2014

Re: Pulse width timing violation even with the same CLOCK_DELAY_GROUP

hi,seems I still met hold timing violations after clock_root constraints were added.

my related constraints are:

create_generated_clock -name {clk_oserdes} [get_pins {u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/mmcme3_adv_inst/CLKOUT1}]
create_generated_clock -name {clk_oserdes_div} [get_pins {u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/clkout1_div_buf/O}]
##create_generated_clock -name {core_clk} [get_pins {*/u_NV_HSTDM_ga10x_sendclk/inst/clkout1_div_buf/O}]

 

set_property CLOCK_DELAY_GROUP MUX_and_BUFGCE [get_nets of [get_pins {u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/mmcme3_adv_inst/CLKOUT1}]]
set_property CLOCK_DELAY_GROUP MUX_and_BUFGCE [get_nets of [get_pins u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/clkout1_div_buf/O]]

set_property USER_CLOCK_ROOT X2Y3 [get_nets of [get_pins {u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/mmcme3_adv_inst/CLKOUT1}]]
set_property USER_CLOCK_ROOT X2Y3 [get_nets of [get_pins u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/clkout1_div_buf/O]]

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Historian
Historian
256 Views
Registered: ‎01-23-2009

Re: Pulse width timing violation even with the same CLOCK_DELAY_GROUP

Your commands are not correct - I suspect they are just typos when you pasted them here. In the set_property commands, the should be:

set_property CLOCK_DELAY_GROUP MUX_and_BUFGCE [get_nets -of [get_pins {u_NV_hstdm_sourcesyn_send/u_NV_HSTDM_ga10x_sendclk/inst/mmcme3_adv_inst/CLKOUT1}]]

your commands are missing the dash before the word of

Other than this, I don't see anything obvious. If this still doesn't fix the timing violation, I have no more suggestions for you... This seems to be a problem in UltraScale - the combination of the on-chip variation pessimism of the tool with the very tight skew requirement between CLK and CLKDIV of the ISERDES/OSERDES makes the pulse width check impossible to meet (at least under some circumstances). 

It is up to Xilinx to figure out where to go from here - if you have followed the XAPP note in the referenced post (and it looks like you did) and you still fail timing, then there is no solution to this problem...

Avrum

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Adventurer
Adventurer
246 Views
Registered: ‎08-15-2014

Re: Pulse width timing violation even with the same CLOCK_DELAY_GROUP

hi,Avrumw,

yes, you're correct, it's just a typo here. 

But I still get the pulse width timing violation here. even with same clock_delay_group and clock_root.

Waiting for guys from xlinx to help on this.

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