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jw_l3harris
Observer
Observer
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Registered: ‎12-09-2019

QSPI Input/Output Constraints with Inverted Flash Clock

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I am having trouble properly analyzing and constraining a system-synchronous QSPI interface interface to an Ultrascale+ device due to the method in which the clock is distributed to the external flash device. 

In a typical case, the internal logic and SPI clock are the same frequency and phase, so the output delay constraints are:

set_output_delay -clock cclk -max trce_dly_max+tsu [get_ports outSpiMosi]
set_output_delay -clock cclk -min trce_dly_min-thd [get_ports outSpiMosi]

and input:

set_input_delay -clock cclk -max tco_max+trce_dly_max [get_ports inSpiMiso] <-clock_fall>
set_input_delay -clock cclk -min tco_min+trce_dly_min [get_ports inSpiMiso] <-clock_fall>

However in the current design, the internal SPI logic clock is routed to an ODDR which inverts it and that clock is routed to the external flash. I believe since the clock is inverted (or delayed by 180 degrees), I would add half of the clock period time to my input and output delays.

 

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avrumw
Expert
Expert
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Registered: ‎01-23-2009

You say the interface is system synchronous - so a clock is generated on the board and distributed to the FPGA and to the QSPI, but the QSPI is inverted? (So you have some kind of clock distribution chip that is also able to do the inversion)?

As is the case with all specifications for an I/O, describe it as accurately as you can and let the tools take care of it.

If the clock in question is 100MHz (just as a place holder) then you would have TWO clocks to specify

create_clock -name CCK -period 10.0 -waveform {0 5.0} [get_ports <FPGA_port>]
create_clock -name QSPI_CLK -period 10.0 -waveform {5.0 0}; # This is a virtual clock used for the QPSI

These two clocks are identical except that the falling edge of one occurs at the rising edge of the other (and vice versa). In Vivado all clocks are considered synchronous by default - therefore, the tools will process static timing paths between them as synchronous. 

Now you can specify the input and output delays of the QSPI with respect to the clock it receives (QSPI_CLK). Since the tool understands the relationship between CCLK and QSPI_CLK, the timing analysis will be done correctly - including the understanding that the clocks are inverted between the two.

Avrum

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avrumw
Expert
Expert
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Registered: ‎01-23-2009

You say the interface is system synchronous - so a clock is generated on the board and distributed to the FPGA and to the QSPI, but the QSPI is inverted? (So you have some kind of clock distribution chip that is also able to do the inversion)?

As is the case with all specifications for an I/O, describe it as accurately as you can and let the tools take care of it.

If the clock in question is 100MHz (just as a place holder) then you would have TWO clocks to specify

create_clock -name CCK -period 10.0 -waveform {0 5.0} [get_ports <FPGA_port>]
create_clock -name QSPI_CLK -period 10.0 -waveform {5.0 0}; # This is a virtual clock used for the QPSI

These two clocks are identical except that the falling edge of one occurs at the rising edge of the other (and vice versa). In Vivado all clocks are considered synchronous by default - therefore, the tools will process static timing paths between them as synchronous. 

Now you can specify the input and output delays of the QSPI with respect to the clock it receives (QSPI_CLK). Since the tool understands the relationship between CCLK and QSPI_CLK, the timing analysis will be done correctly - including the understanding that the clocks are inverted between the two.

Avrum

View solution in original post

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