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ankit10001
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Registered: ‎05-28-2013

Question about maximum combinational path delay

I have designed a single bit full adder and after synthesis the maximum combinational path delay is 5.776 ns. When i use registers for input and output the minimum period says 1.718 ns ( max. frequency 582.072 MHz). My question is how can the minimum period be less than the maximum combinational path delay? Isnt it supposed to be greater than or atleast equal to maximum combinational path delay?

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gszakacs
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Registered: ‎08-14-2007

When you run a design through synthesis, the default is to add IO buffers to the top level design

ports (FPGA pins).  The maximum combinatorial delay includes the IO buffer timing, i.e. it

reports the maximum delay from FPGA input pin to the FPGA output pin.  When you add registers

to the input and output, the path no longer includes any IO elements, and as you can see by the

results you get much faster timing.  This is why it's a good idea to have input and output registers

when you want to determine internal logic delays.

-- Gabor
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ankit10001
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Is it possible to see the IO buffer timings in the post PAR timing report? Is it the same as the OFFSET IN and OFFSET OUT  time when using registered input/outputs?

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gszakacs
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Registered: ‎08-14-2007

You can see all components of a timing path in the post-PAR timing report.  By default,

the report only shows paths that are constrained, and only the 3 worst case for each

constraint.  You can change the report settings to also report unconstrained paths

as well as to increase the number of paths and/or endpoints displayed for each

constraint.

 

The "offset in" (setup to clock) and "offset out" (clock to output) paths are affected by

the IO buffer delays, but that is not the sole component of the delay.

 

Also note that timing reported by synthesis is only an estimate, although it is useful

to look at relative timing (i.e. does making this change help or hurt the timing).

-- Gabor
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ankit10001
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So basically max. combinational path delay includes I/O buffer delays but when we use registered I/O, buffer delays are excluded and we get a higher frequency. But the actual frequency should be lesser than this as the time taken for data to appear at input register and from output register to pad would limit the frequency of operation.

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gszakacs
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Registered: ‎08-14-2007


@ankit10001 wrote:

So basically max. combinational path delay includes I/O buffer delays but when we use registered I/O, buffer delays are excluded and we get a higher frequency. But the actual frequency should be lesser than this as the time taken for data to appear at input register and from output register to pad would limit the frequency of operation.


All delays reported are pin to pin.  Periods reported are only for internal paths from Q to D of fabric or IOB flops, but not off the chip.  Whenever you go off chip there are IO buffers in the path.  In a real system you need to make sure that the input and output offsets meet the needs of external boad components that are not known by the Xilinx tools.  That's why you need to enter the requirements as constraints.  And even with these constraints, the Xilinx tools don't know what the maximum board-level operating frequency will be, so it only reports internal freuencies.  Normally you have a board level frequency requirement, which you enter as a PERIOD constraint.  You also make sure that the offset in and out constraints are sufficient to meet the needs of the other board components at this frequency.

 

If you're trying to get performance numbers on an internal piece of logic without regard to board-level requirements, the easiest way is to place at least two registers before and after the internal logic.  This allows the tools to provide the shortest possible routes from (fabric) flip-flops to the internal logic.  Even then, just running through the tools with no constraints will not necessarily give you the best case delays, so you need to set a PERIOD constraint as a target.

-- Gabor
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fnohr10
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Registered: ‎04-25-2013

You write

When you run a design through synthesis, the default is to add IO buffers to the top level design ports (FPGA pins).

 

I am doing some timing simulation for different circuits for my semester project, so if you have some material on the statement above, I am very interested. Maybe a link to one of the many Xilinx .pdf's where I can find further information.

Thank you!

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