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liwenrui
Observer
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Registered: ‎06-24-2011

Question about the offset in and offset out in the training "Global Timing Constraints"

I just learned the trainning Global Timing Constraints and that is great.

 

I just have a question about a part of the training shown below.  In this diagram, we are told there was 4 ns for the upstream device output so the offset in is 6 ns for 100MHz.  My question is:  how do we get this information like 4 ns or 5 ns?

 

For the upstream device tp403 I have,  I only have this from the datesheet:

 

  Tsu(1,2, min)=1ns, Th(1,2, min)=1ns.

 

In this case, what is the offset in? Assume the system clk is 100MHz.

 

TP403 timing:

Untitled.png

 

The page from training:

 

Untitled.png

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liwenrui
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Registered: ‎06-24-2011

And what is the constraint line for this case?  Is the following correct?  

 

OFFSET = IN 9 ns VALID 1 ns BEFORE “ODCK”

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bassman59
Historian
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Registered: ‎02-25-2008


@liwenrui wrote:

And what is the constraint line for this case?  Is the following correct?  

OFFSET = IN 9 ns VALID 1 ns BEFORE “ODCK”


That constraint tells the tools that the signal in question will be valid 9 ns before the active edge of the clock (which you must specify) and it will remain valid for 1 ns.

 

As to whether it's correct for your given situation, I don't know since I didn't really read your homework assignment. My guess is ... that it's not. (Ask yourself why.)

----------------------------Yes, I do this for a living.
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liwenrui
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Registered: ‎06-24-2011

Now I figured out it.

For ock_inv = low:

net odck TNM_NET = "tm_odck";
timespec ts_odck = period "tm_odck" 10 ns low 50%
offset = in 1 ns valid 2 ns before "tm_odck" before "tm_odck" falling
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liwenrui
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Registered: ‎06-24-2011

Is the above right, any one?

 

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bassman59
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Registered: ‎02-25-2008


@liwenrui wrote:

Is the above right, any one?

 


For an upstream device feeding the FPGA's inputs, the only parameter of interest is clock-to-out time. 

And that assumes that the clock in question is the same one which clocks the FPGA's input.

----------------------------Yes, I do this for a living.
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nsshah1
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Registered: ‎02-12-2013

Above post is right!

 

You need to post the clk to output times (min and max delay of data start to clock edge). This will determine your offset in constraint for the FPGA.

 

The tsu/thld is completely irrelevant as that part has no clue what the ILOGIC Tsu/Th for the FPGA is. Repost the clk-Q data.

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