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Adventurer
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Registered: ‎05-12-2014

Question concerning XPM_CDC_SINGLE in AR# 67738

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Hello, AR# 67738 explains the Tcl constraint behavior for XPM_CDC_SINGLE. It says:

 

"1) The set_false_path constraint is applied when both the src_clk and dest_clk are defined and they are not the same. This is the most common use case for CDC modules."

 

My question is concerning the fact that the src_clk input to the XPM_CDC_SINGLE macro is not listed as "required" in UG953. The table in the user guide says to tie the src_clk input to 0 if it is unused, and also that the port is "unused when SRC_INPUT_REG = 0." If I am not using a source input register (SRC_INPUT_REG = 0) and I tie the src_clk input to 0, does that mean that the necessary timing constraints will not be generated for the CDC? That seems to be what the AR is indicating, but if that were the case, why wouldn't the src_clk input be "required" in UG953? After all, what good is a CDC macro if it doesn't generate the necessary timing constraints?

 

Thanks as always,

Dave

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Mentor
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Registered: ‎02-24-2014

Re: Question concerning XPM_CDC_SINGLE in AR# 67738

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I agree that the statement is incomplete..  I just tested this xpm in 2018.1:

 

   xpm_cdc_single_inst : xpm_cdc_single
   generic map (
      DEST_SYNC_FF => 2,     -- DECIMAL; range: 2-10
      INIT_SYNC_FF => 0,     -- DECIMAL; integer; 0=disable simulation init values, 1=enable simulation init
                             -- values
      SIM_ASSERT_CHK => 0,   -- DECIMAL; integer; 0=disable simulation messages, 1=enable simulation messages
      SRC_INPUT_REG => 0     -- DECIMAL; integer; 0=do not register input, 1=register input
   )
   port map (
      dest_out => test_out,  -- 1-bit output: src_in synchronized to the destination clock domain. This output
                             -- is registered.

      dest_clk => ref_clk,   -- 1-bit input: Clock signal for the destination clock domain.
      src_clk => '0',        -- 1-bit input: optional; required when SRC_INPUT_REG = 1
      src_in => test_in      -- 1-bit input: Input signal to be synchronized to dest_clk domain.
   );

The false path constraint does get set properly despite the missing source clock.

 

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Registered: ‎02-24-2014

Re: Question concerning XPM_CDC_SINGLE in AR# 67738

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Well, let's look at the TCL script giving the scoped constraints for the XPM_CDC_SINGLE macro.

 

# Scoped constraints for xpm_cdc_single
set src_clk  [get_clocks -quiet -of [get_ports src_clk]]
set dest_clk [get_clocks -quiet -of [get_ports dest_clk]]

if {($src_clk != $dest_clk) || ($src_clk == "" && $dest_clk == "")} {
    set_false_path -to [get_cells syncstages_ff_reg[0]]
} elseif {$src_clk != "" && $dest_clk != ""} {
    common::send_msg_id "XPM_CDC_SINGLE: TCL-1000" "WARNING" "The source and destination clocks are the same. \n     Instance: [current_instance .] \n  This will add unnecessary latency to the design. Please check the design for the following: \n 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. \n 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message."
}

As you can see... the first statement is to get the source clock connected to the port "src_clk".    If it's grounded, the value for $src_clk will be "".    This should match the first condition in the "if" test below, since "" won't match any valid $dest_clk.  So the false path constraint should be applied to the input of the synchronizer.  

 

quod erat demonstrandum

 

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Registered: ‎05-12-2014

Re: Question concerning XPM_CDC_SINGLE in AR# 67738

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@jmcclusk, thank you for your reply and for showing the TCL script. Your explanation makes sense. Based on that, do you agree with me that the following statement from the answer record is at least incomplete, if not incorrect? (My emphasis is added in bold.) Or do you interpret the statement differently?

 

1) The set_false_path constraint is applied when both the src_clk and dest_clk are defined and they are not the same.

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Re: Question concerning XPM_CDC_SINGLE in AR# 67738

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I agree that the statement is incomplete..  I just tested this xpm in 2018.1:

 

   xpm_cdc_single_inst : xpm_cdc_single
   generic map (
      DEST_SYNC_FF => 2,     -- DECIMAL; range: 2-10
      INIT_SYNC_FF => 0,     -- DECIMAL; integer; 0=disable simulation init values, 1=enable simulation init
                             -- values
      SIM_ASSERT_CHK => 0,   -- DECIMAL; integer; 0=disable simulation messages, 1=enable simulation messages
      SRC_INPUT_REG => 0     -- DECIMAL; integer; 0=do not register input, 1=register input
   )
   port map (
      dest_out => test_out,  -- 1-bit output: src_in synchronized to the destination clock domain. This output
                             -- is registered.

      dest_clk => ref_clk,   -- 1-bit input: Clock signal for the destination clock domain.
      src_clk => '0',        -- 1-bit input: optional; required when SRC_INPUT_REG = 1
      src_in => test_in      -- 1-bit input: Input signal to be synchronized to dest_clk domain.
   );

The false path constraint does get set properly despite the missing source clock.

 

Don't forget to close a thread when possible by accepting a post as a solution.

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