01-12-2014 06:30 PM
Now my quesiton is the constraint on the From-to is a constant delay or only a maximum delay when I give a constranit in th UCF or editor. For instance, when I give a 10ns delay for a constraint on 'PAD to FF', the timing report only told me MAX Delay is 6.423ns. Therefore I am very confused. Is 10ns a constant value or maximum value? Or if when the gate-logic is less than 10ns, some man-made delay will be added, won't it?
If indeed it is a constant delay, who can't tell me how to read the timing report?
Maybe this is not big problem to you, experts. Please provide some points to me. :)
01-12-2014 06:37 PM
The value is maximum delay. The tool will make effort to obey the constraint so that the path delay doesn't exceed 10 ns.
The max delay shown in timing report is the performance that the tool can achieve. There's some margin (positive slack) here.
ISE timing doesn't support minimum delay.
01-12-2014 07:00 PM
01-12-2014 07:12 PM
There's no way to implement a fixed delay in FPGA. Considering the PVT variation, the path delay will vary between a range in hardware.
For a PAD TO FF path, the most viable way to get a consistent path delay is to place the FF in IOB. Of cousre the FF needs to be I/O register (i.e. there's no combinatorial logic between pad and FF). This ensures dedicated routing resource to be utilized.
01-12-2014 07:29 PM
01-12-2014 08:51 PM
The slow exception section gives another method to define multi-cycle constraints.
The path between FFs that have CE pin can have requirement of 2 or more cycles rather than a single cycle.
Anyway the delay value is a guided max delay for implementation tool. It will by no means result in a fixed delay.
You can preserve the routing delay as much as possible by locking down the associated components and apply directed routing constraint (DIRT).