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Registered: ‎01-15-2013

RMII timing analysis on Zynq 7000


I have a similar problem to one discussed in this post : 

Basically, I am driving a PHY with RMII interface. I am feeding a RMII output clock with a phase shift of -18 degrees from a PLL, enough to meet hold requirements of the PHY (Setup = 3.7 ns and hold = 1.7ns). The phase shifted clock is fed from ODDR and the TX_DATA flops are forced in IOB.The speed grade of FPGA is 1 and tool used is Vivado 2018.3. Input and output constraints were added to the SDC as follows : 

create_generated_clock -name rmii_clock -source [get_pins base_zynq_i/oddr_0/clk_in] -multiply_by 1 -divide_by 1 [get_ports rmii_ref_clk]
set_output_delay -clock [get_clocks rmii_clock] -max 5.000 [get_ports {{rmii_rtl_txd[0]} {rmii_rtl_txd[1]} rmii_rtl_tx_en}]
set_output_delay -clock [get_clocks rmii_clock] -min -3.000 [get_ports {{rmii_rtl_txd[0]} {rmii_rtl_txd[1]} rmii_rtl_tx_en}]

set_property IOB TRUE [get_ports rmii_rtl_txd*];

set_input_delay -max 15 -clock [get_clocks rmii_clock] [get_ports rmii_rtl_rxd*]
set_input_delay -min 3 -clock [get_clocks rmii_clock] [get_ports rmii_rtl_rxd*]

set_property IOB TRUE [get_ports rmii_rtl_rxd*];

The main problem is that clk to ouput for the PHY is quite high (2 to 14 ns) and period is 20 ns. So data valid window is quite less. As I don't have a return clock from PHY, I am limited to sampling data with the system clock. The design fails timing on the RX side on the input with a huge slack -16 ns, so obviously there is something wrong with my constraints. I don't understand some of the delay reported by the tool especially the data path delay highlighted in figure 2. 

Any help will be appreciated. 



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