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Visitor ted_130706
Visitor
249 Views
Registered: ‎11-07-2018

Re: Can not keep timing of maximum clock skew inside the MIG

I also tried Vivado 2018.3, but the results were the same.

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Moderator
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Registered: ‎11-28-2016

Re: Can not keep timing of maximum clock skew inside the MIG

Hello @ted_130706,

If this is happening then most likely you have a pretty big design and the FPGA doesn't have enough routing resources to meet timing.  I would try different implementation directives settings in Vivado to see if that helps. You could also try reducing the logic in your design.  Overall this isn't anything IP specific.

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