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572 Views
Registered: ‎10-31-2018

Reducing long net delay routing

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I've been running into long net delays when implementing my project. The data paths seem to be on the same hierarchical level. However, on the device tab it appears that the datapath has been routed all over the die. I've tried using pblocks to group the logic into one clock region. 

 

The datapath should only be clocked by the U59/U16/O clock, as in the constraints file it is a generated clock from NET2555 divided by 2.

 

What can I do to minimize this weird net routing?

 

Data_path.jpg
device_view.jpg
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528 Views
Registered: ‎01-22-2015

Re: Reducing long net delay routing

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@dalepelletron

 

In the constraints file you wrote:

     #these generated clocks are created by counters/flip flops clocked by the 64 or 32MHz clocks

 

It seems that you are generating and routing some slow clocks in the FPGA fabric. This is not recommended as explained by avrumw in <this> post.  Be sure to read his description of the BUFGCE/BUFHCE method for creating slow clocks, which will keep routing of the clocks in the clock tree and help your design pass timing analysis.

 

Mark

 

 

5 Replies
Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Reducing long net delay routing

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the tools run to meet your timing constraints and stop

 

what are your timing constraints ?

 

 

out of interest, why are you looking at pblocks ?

  you dont seem to be very full, are you designing a re usable placed block ?

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Registered: ‎10-31-2018

Re: Reducing long net delay routing

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I've been trying to port a Spartan II design to 7 Series, and I'm not as experienced with XDC. I will attached what I've been using. After searching these forums most solution to long net delays seem to be phys_opt_design and pblocks. I thought I defined my clocks and outputs correctly, but honestly the last design I ported was simpler. 

 

#analog_control_main.xdc
#For Artix7 package: XC7A15-IFTG256C
#Last update: 10/9/18

#**Clock Constraints**
#this is the primary clock for all logic, it goes through the MMCM and creates 64 & 32MHz clocks
create_clock -period 31.250 -name pCLK [get_ports pCLK]
set_property PACKAGE_PIN N14 [get_ports pCLK]
set_property IOSTANDARD LVCMOS33 [get_ports pCLK]

#jtag clocks at 6MHz maximum
#create_clock -period 166.667 -name NET1918 -waveform {0.000 83.334} [get_pins U97__0/DRCK]

#these generated clocks are created by counters/flip flops clocked by the 64 or 32MHz clocks
create_generated_clock -name U4/U8/U8/Q -source [get_pins U4/U11/CLKOUT0] -divide_by 4096 [get_pins U4/U8/U8/Q]
create_generated_clock -name U4/U7/U7/Q -source [get_pins U4/U11/CLKOUT0] -divide_by 32768 [get_pins U4/U7/U7/Q]
create_generated_clock -name U4/U6/U8/Q -source [get_pins U4/U11/CLKOUT0] -divide_by 1048576 [get_pins U4/U6/U8/Q]
create_generated_clock -name U4/U5/U5/Q -source [get_pins U4/U11/CLKOUT0] -divide_by 2097152 [get_pins U4/U5/U5/Q]
create_generated_clock -name U4/U5/U7/Q -source [get_pins U4/U11/CLKOUT0] -divide_by 8388608 [get_pins U4/U5/U7/Q]
create_generated_clock -name U4/U4/U5/Q -source [get_pins U4/U11/CLKOUT0] -divide_by 33554432 [get_pins U4/U4/U5/Q]

create_generated_clock -name U1/U13/U59/clkd_Clk_enable_reg/Q -source [get_pins U4/U11/CLKOUT1] -divide_by 2 [get_pins U1/U13/U59/clkd_Clk_enable_reg/Q]
create_generated_clock -name U59/U16/O -source [get_pins U4/U11/CLKOUT1] -divide_by 2 [get_pins U59/U16/O]
create_generated_clock -name U59/U17/O -source [get_pins U4/U11/CLKOUT1] -divide_by 2 [get_pins U59/U17/O]
create_generated_clock -name U59/U18/O -source [get_pins U4/U11/CLKOUT1] -divide_by 2 [get_pins U59/U18/O]
create_generated_clock -name U60/U31/O -source [get_pins U4/U11/CLKOUT4] -divide_by 2 [get_pins U60/U31/O]
create_generated_clock -name U60/U32/O -source [get_pins U4/U11/CLKOUT4] -divide_by 2 [get_pins U60/U32/O]
create_generated_clock -name U60/U33/O -source [get_pins U4/U11/CLKOUT4] -divide_by 2 [get_pins U60/U33/O]

#eliminate interaction between clocks
set_clock_groups -asynchronous -group [get_clocks {U4/U4/U5/Q U4/U5/U5/Q U4/U5/U7/Q U4/U6/U8/Q U4/U7/U7/Q U4/U8/U8/Q}] -group [get_clocks NET2555]
set_clock_groups -asynchronous -group [get_clocks {U4/U4/U5/Q U4/U5/U5/Q U4/U5/U7/Q U4/U6/U8/Q U4/U7/U7/Q U4/U8/U8/Q}] -group [get_clocks NET4908]
set_clock_groups -asynchronous -group [get_clocks {U59/U16/O U59/U17/O U59/U18/O}] -group [get_clocks NET2555]
set_clock_groups -asynchronous -group [get_clocks {U60/U31/O U60/U32/O U60/U33/O}] -group [get_clocks NET2555]

#**Set Package Pins**
#I/O bank 14
set_property PACKAGE_PIN R5 [get_ports pRST]
set_property PACKAGE_PIN T5 [get_ports pMZRST]
set_property PACKAGE_PIN M6 [get_ports pCS0_3_CSA]
set_property PACKAGE_PIN N6 [get_ports pLDAC0_3_CSB]
set_property PACKAGE_PIN P6 [get_ports pCS4_7_CSC]
set_property PACKAGE_PIN R7 [get_ports pLDAC4_7_EN0]
set_property PACKAGE_PIN T7 [get_ports pCS8_11_EN1]
set_property PACKAGE_PIN P8 [get_ports pLDAC16_19_CSMZB]
set_property PACKAGE_PIN R8 [get_ports pCS20_23_CSMZC]
set_property PACKAGE_PIN T8 [get_ports pLDAC20_23_EN2]

set_property PACKAGE_PIN N9 [get_ports pDRDY]
set_property PACKAGE_PIN P9 [get_ports pDRDY1]
set_property PACKAGE_PIN T9 [get_ports pDRDY2]
set_property PACKAGE_PIN P10 [get_ports pSDI]
set_property PACKAGE_PIN R10 [get_ports pSDI1]
set_property PACKAGE_PIN T10 [get_ports pSDI2]
set_property PACKAGE_PIN N11 [get_ports pSDO]
set_property PACKAGE_PIN P11 [get_ports pSDO1]
set_property PACKAGE_PIN R11 [get_ports pSDO2]
set_property PACKAGE_PIN N12 [get_ports pSCLK]
set_property PACKAGE_PIN R12 [get_ports pSCLK1]
set_property PACKAGE_PIN T12 [get_ports pSCLK2]

#I/O bank 15
set_property PACKAGE_PIN A13 [get_ports pR_W]
set_property PACKAGE_PIN A14 [get_ports pS1]

set_property PACKAGE_PIN B12 [get_ports {pC[3]}]
set_property PACKAGE_PIN B14 [get_ports {pC[2]}]
set_property PACKAGE_PIN B15 [get_ports {pC[1]}]
set_property PACKAGE_PIN B16 [get_ports {pC[0]}]
set_property PACKAGE_PIN C12 [get_ports {pN[3]}]
set_property PACKAGE_PIN C13 [get_ports {pN[2]}]
set_property PACKAGE_PIN C14 [get_ports {pN[1]}]
set_property PACKAGE_PIN C16 [get_ports {pN[0]}]
set_property PACKAGE_PIN D13 [get_ports {pA[3]}]
set_property PACKAGE_PIN D14 [get_ports {pA[2]}]
set_property PACKAGE_PIN D15 [get_ports {pA[1]}]
set_property PACKAGE_PIN D16 [get_ports {pA[0]}]

set_property PACKAGE_PIN E12 [get_ports {pDATA[7]}]
set_property PACKAGE_PIN E13 [get_ports {pDATA[6]}]
set_property PACKAGE_PIN E15 [get_ports {pDATA[5]}]
set_property PACKAGE_PIN E16 [get_ports {pDATA[4]}]
set_property PACKAGE_PIN F12 [get_ports {pDATA[3]}]
set_property PACKAGE_PIN F13 [get_ports {pDATA[2]}]
set_property PACKAGE_PIN F14 [get_ports {pDATA[1]}]
set_property PACKAGE_PIN F15 [get_ports {pDATA[0]}]

set_property PACKAGE_PIN A9 [get_ports {pModAddr[3]}]
set_property PACKAGE_PIN B9 [get_ports {pModAddr[2]}]
set_property PACKAGE_PIN C9 [get_ports {pModAddr[1]}]
set_property PACKAGE_PIN D9 [get_ports {pModAddr[0]}]

set_property PACKAGE_PIN A10 [get_ports pT_R]

#I/O bank 34
set_property PACKAGE_PIN L4 [get_ports pE2RST]
set_property PACKAGE_PIN L5 [get_ports pWP]
set_property PACKAGE_PIN M1 [get_ports pLDE2]
set_property PACKAGE_PIN M2 [get_ports pE2CLK]
set_property PACKAGE_PIN M4 [get_ports pE2SDI]
set_property PACKAGE_PIN M5 [get_ports pE2SDO]
set_property PACKAGE_PIN N1 [get_ports pMZE2RST]
set_property PACKAGE_PIN N2 [get_ports pLDMZE2]

set_property PACKAGE_PIN P1 [get_ports pI_O_select]
set_property PACKAGE_PIN P3 [get_ports pMezz_I_select]
set_property PACKAGE_PIN P4 [get_ports pMezz_O_select]

#I/O bank 35
set_property PACKAGE_PIN B6 [get_ports pMYWR]
set_property PACKAGE_PIN C6 [get_ports pMYRD]
set_property PACKAGE_PIN D6 [get_ports pN_LED]
set_property PACKAGE_PIN A7 [get_ports pH_Watchdog_Touch]
set_property PACKAGE_PIN B7 [get_ports pTimeOut_LED]

set_property PACKAGE_PIN A2 [get_ports {pLED[0]}]
set_property PACKAGE_PIN A3 [get_ports {pLED[1]}]
set_property PACKAGE_PIN A4 [get_ports {pLED[2]}]
set_property PACKAGE_PIN A5 [get_ports {pLED[3]}]
set_property PACKAGE_PIN B1 [get_ports {pLED[4]}]
set_property PACKAGE_PIN B2 [get_ports {pLED[5]}]
set_property PACKAGE_PIN B4 [get_ports {pLED[6]}]
set_property PACKAGE_PIN B5 [get_ports {pLED[7]}]
set_property PACKAGE_PIN C1 [get_ports {pLED[8]}]
set_property PACKAGE_PIN C2 [get_ports {pLED[9]}]
set_property PACKAGE_PIN C3 [get_ports {pLED[10]}]
set_property PACKAGE_PIN C4 [get_ports {pLED[11]}]
set_property PACKAGE_PIN D1 [get_ports {pLED[12]}]
set_property PACKAGE_PIN D3 [get_ports {pLED[13]}]
set_property PACKAGE_PIN D4 [get_ports {pLED[14]}]
set_property PACKAGE_PIN D5 [get_ports {pLED[15]}]

set_property PACKAGE_PIN E1 [get_ports {pMON_sel[0]}]
set_property PACKAGE_PIN E2 [get_ports {pMON_sel[1]}]
set_property PACKAGE_PIN E3 [get_ports {pMON_sel[2]}]
set_property PACKAGE_PIN E5 [get_ports {pMON_sel3[0]}]
set_property PACKAGE_PIN F2 [get_ports {pMON_sel3[1]}]
set_property PACKAGE_PIN F3 [get_ports {pMON_sel3[2]}]
set_property PACKAGE_PIN F4 [get_ports pMON_sel_OR]

set_property PACKAGE_PIN H1 [get_ports pLamp_Test_In]
set_property PACKAGE_PIN H2 [get_ports pLamp_Test]

#**Set IO standards**
#I/O bank 14
set_property IOSTANDARD LVCMOS33 [get_ports pRST]
set_property IOSTANDARD LVCMOS33 [get_ports pCS0_3_CSA]
set_property IOSTANDARD LVCMOS33 [get_ports pLDAC0_3_CSB]
set_property IOSTANDARD LVCMOS33 [get_ports pCS4_7_CSC]
set_property IOSTANDARD LVCMOS33 [get_ports pLDAC4_7_EN0]
set_property IOSTANDARD LVCMOS33 [get_ports pCS8_11_EN1]
set_property IOSTANDARD LVCMOS33 [get_ports pLDAC8_11]
set_property IOSTANDARD LVCMOS33 [get_ports pCS12_15]
set_property IOSTANDARD LVCMOS33 [get_ports pLDAC12_15]
set_property IOSTANDARD LVCMOS33 [get_ports pCS16_19_CSMZA]
set_property IOSTANDARD LVCMOS33 [get_ports pLDAC16_19_CSMZB]
set_property IOSTANDARD LVCMOS33 [get_ports pCS20_23_CSMZC]
set_property IOSTANDARD LVCMOS33 [get_ports pLDAC20_23_EN2]

#I/O bank 15
set_property IOSTANDARD LVCMOS33 [get_ports pR_W]
set_property IOSTANDARD LVCMOS33 [get_ports pS1]
set_property IOSTANDARD LVCMOS33 [get_ports {pC[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pN[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pA[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pDATA[*]}]

set_property IOSTANDARD LVCMOS33 [get_ports {pModAddr[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports pT_R]

#I/O bank 34
set_property IOSTANDARD LVCMOS33 [get_ports pE2RST]
set_property IOSTANDARD LVCMOS33 [get_ports pWP]
set_property IOSTANDARD LVCMOS33 [get_ports pLDE2]
set_property IOSTANDARD LVCMOS33 [get_ports pE2CLK]
set_property IOSTANDARD LVCMOS33 [get_ports pE2SDI]
set_property IOSTANDARD LVCMOS33 [get_ports pE2SDO]
set_property IOSTANDARD LVCMOS33 [get_ports pMZE2RST]
set_property IOSTANDARD LVCMOS33 [get_ports pLDMZE2]

set_property IOSTANDARD LVCMOS33 [get_ports pI_O_select]
set_property IOSTANDARD LVCMOS33 [get_ports pMezz_I_select]
set_property IOSTANDARD LVCMOS33 [get_ports pMezz_O_select]

#I/O bank 35
set_property IOSTANDARD LVCMOS33 [get_ports pMYRD]
set_property IOSTANDARD LVCMOS33 [get_ports pMYWR]
set_property IOSTANDARD LVCMOS33 [get_ports pN_LED]
set_property IOSTANDARD LVCMOS33 [get_ports pH_Watchdog_Touch]
set_property IOSTANDARD LVCMOS33 [get_ports pTimeOut_LED]
set_property IOSTANDARD LVCMOS33 [get_ports {pLED[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pMON_sel[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pMON_sel3[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports pMON_sel_OR]

set_property IOSTANDARD LVCMOS33 [get_ports pLamp_Test_In]
set_property IOSTANDARD LVCMOS33 [get_ports pLamp_Test]

#**Set Input Delays**
set_input_delay -clock NET2555 -max 4.000 [get_ports {pDATA[*]}]
set_input_delay -clock NET2555 -min 1.300 [get_ports {pDATA[*]}]
set_input_delay -clock NET2555 -max 6.500 [get_ports {pC[*]}]
set_input_delay -clock NET2555 -min 1.500 [get_ports {pC[*]}]
set_input_delay -clock NET2555 -max 6.500 [get_ports {pN[*]}]
set_input_delay -clock NET2555 -min 1.500 [get_ports {pN[*]}]
set_input_delay -clock NET2555 -max 6.500 [get_ports {pA[*]}]
set_input_delay -clock NET2555 -min 1.500 [get_ports {pA[*]}]
set_input_delay -clock NET2555 -max 6.500 [get_ports pR_W]
set_input_delay -clock NET2555 -min 1.500 [get_ports pR_W]
set_input_delay -clock NET2555 -max 6.500 [get_ports pS1]
set_input_delay -clock NET2555 -min 1.500 [get_ports pS1]
set_input_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q -max 6.000 [get_ports pE2SDO]
set_input_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q -min 0.000 [get_ports pE2SDO]
set_input_delay -clock U60/U31/O -max 80.000 [get_ports pSDO]
set_input_delay -clock U60/U31/O -min 0.000 [get_ports pSDO]
set_input_delay -clock U60/U32/O -max 80.000 [get_ports pSDO1]
set_input_delay -clock U60/U32/O -min 0.000 [get_ports pSDO1]
set_input_delay -clock U60/U33/O -max 80.000 [get_ports pSDO2]
set_input_delay -clock U60/U33/O -min 0.000 [get_ports pSDO2]
set_input_delay -clock NET2559 -max 6.500 [get_ports pDRDY]
set_input_delay -clock NET2559 -min 1.500 [get_ports pDRDY]
set_input_delay -clock NET2559 -max 6.500 [get_ports pDRDY1]
set_input_delay -clock NET2559 -min 1.500 [get_ports pDRDY1]
set_input_delay -clock NET2559 -max 6.500 [get_ports pDRDY2]
set_input_delay -clock NET2559 -min 1.500 [get_ports pDRDY2]

#**Set Output Delays**
set_output_delay -clock NET2555 -max 6.500 [get_ports {pDATA[*]}]
set_output_delay -clock NET2555 -min 1.500 [get_ports {pDATA[*]}]
set_output_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q 5.000 [get_ports pWP]
set_output_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q 5.000 [get_ports pLDE2]
set_output_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q 5.000 [get_ports pLDMZE2]
set_output_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q 3.000 [get_ports pE2CLK]
set_output_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q -max 3.000 [get_ports pE2SDI]
set_output_delay -clock U1/U13/U59/clkd_Clk_enable_reg/Q -min 2.000 [get_ports pE2SDI]
set_output_delay -clock NET2555 -max 4.000 [get_ports pT_R]
set_output_delay -clock NET2555 -min 1.300 [get_ports pT_R]

set_output_delay -clock U59/U16/O -max 7.000 [get_ports pCS0_3_CSA]
set_output_delay -clock U59/U16/O -min -7.000 [get_ports pCS0_3_CSA]
set_output_delay -clock U59/U16/O -max 7.000 [get_ports pLDAC0_3_CSB]
set_output_delay -clock U59/U16/O -min -12.000 [get_ports pLDAC0_3_CSB]
set_output_delay -clock U59/U16/O -max 7.000 [get_ports pCS4_7_CSC]
set_output_delay -clock U59/U16/O -min -7.000 [get_ports pCS4_7_CSC]
set_output_delay -clock U59/U16/O -max 7.000 [get_ports pLDAC4_7_EN0]
set_output_delay -clock U59/U16/O -min -12.000 [get_ports pLDAC4_7_EN0]
set_output_delay -clock U59/U17/O -max 7.000 [get_ports pCS8_11_EN1]
set_output_delay -clock U59/U17/O -min -7.000 [get_ports pCS8_11_EN1]
set_output_delay -clock U59/U17/O -max 7.000 [get_ports pLDAC8_11]
set_output_delay -clock U59/U17/O -min -12.000 [get_ports pLDAC8_11]
set_output_delay -clock U59/U17/O -max 7.000 [get_ports pCS12_15]
set_output_delay -clock U59/U17/O -min -7.000 [get_ports pCS12_15]
set_output_delay -clock U59/U17/O -max 7.000 [get_ports pLDAC12_15]
set_output_delay -clock U59/U17/O -min -12.000 [get_ports pLDAC12_15]
set_output_delay -clock U59/U18/O -max 7.000 [get_ports pCS16_19_CSMZA]
set_output_delay -clock U59/U18/O -min -7.000 [get_ports pCS16_19_CSMZA]
set_output_delay -clock U59/U18/O -max 7.000 [get_ports pLDAC16_19_CSMZB]
set_output_delay -clock U59/U18/O -min -12.000 [get_ports pLDAC16_19_CSMZB]
set_output_delay -clock U59/U18/O -max 7.000 [get_ports pCS20_23_CSMZC]
set_output_delay -clock U59/U18/O -min -7.000 [get_ports pCS20_23_CSMZC]
set_output_delay -clock U59/U18/O -max 7.000 [get_ports pLDAC20_23_EN2]
set_output_delay -clock U59/U18/O -min -12.000 [get_ports pLDAC20_23_EN2]

set_output_delay -clock U59/U16/O -max 7.000 [get_ports pSDI]
set_output_delay -clock U59/U16/O -min -7.000 [get_ports pSDI]
set_output_delay -clock U59/U17/O -max 7.000 [get_ports pSDI1]
set_output_delay -clock U59/U17/O -min -7.000 [get_ports pSDI1]
set_output_delay -clock U59/U18/O -max 7.000 [get_ports pSDI2]
set_output_delay -clock U59/U18/O -min -7.000 [get_ports pSDI2]

set_output_delay -clock NET2555 1.500 [get_ports pSCLK]
set_output_delay -clock NET2555 1.500 [get_ports pSCLK1]
set_output_delay -clock NET2555 1.500 [get_ports pSCLK2]

#**Set Timing Exceptions**
#input pins false paths
set_false_path -from [get_ports pI_O_select] -to [all_registers]
set_false_path -from [get_ports pMezz_I_select] -to [all_registers]
set_false_path -from [get_ports pMezz_O_select] -to [all_registers]
set_false_path -from [get_ports {pModAddr[*]}] -to [all_registers]
set_false_path -from [get_ports pLamp_Test_In] -to [all_registers]

#interal false paths
set_false_path -from [get_pins U2/U7_ARRAY*/C] -to [all_registers]
set_false_path -from [get_pins U2/U8/C] -to [all_registers]
set_false_path -from [get_pins U2/U9/C] -to [all_registers]
set_false_path -from [get_pins U2/U15/C] -to [all_registers]
set_false_path -from [get_pins U2/U7_ARRAY*/C] -to [all_outputs]
set_false_path -from [get_pins U2/U8/C] -to [all_outputs]
set_false_path -from [get_pins U2/U9/C] -to [all_outputs]
set_false_path -from [get_pins U2/U15/C] -to [all_outputs]

#output pins false paths
set_false_path -from [all_registers] -to [get_ports pTimeOut_LED]
set_false_path -from [all_registers] -to [get_ports pN_LED]
set_false_path -from [all_registers] -to [get_ports pMYRD]
set_false_path -from [all_registers] -to [get_ports pMYWR]
set_false_path -from [all_registers] -to [get_ports {pLED[*]}]
set_false_path -from [all_registers] -to [get_ports pLamp_Test]
set_false_path -from [all_registers] -to [get_ports pE2RST]
set_false_path -from [all_registers] -to [get_ports pMZE2RST]
set_false_path -from [all_registers] -to [get_ports pRST]
set_false_path -from [all_registers] -to [get_ports pMZRST]
set_false_path -from [all_registers] -to [get_ports {pMON_sel[*]}]
set_false_path -from [all_registers] -to [get_ports {pMON_sel3[*]}]
set_false_path -from [all_registers] -to [get_ports pMON_sel_OR]

#overide delay for 8MHz KBUS timing
set_max_delay -from [all_registers] -to [get_ports {pDATA[*]}] 62.500
set_max_delay -from [all_registers] -to [get_ports pT_R] 62.500

#overide delay for 32MHz flash memory and DAC, half clock period. Use max delay for DACs, as the ADC's are 8 times slower
set_max_delay -from [all_registers] -to [get_ports pE2CLK] 15.625
set_max_delay -from [all_registers] -to [get_ports pE2SDI] 15.625
set_max_delay -from [all_registers] -to [get_ports pWP] 15.625
set_max_delay -from [all_registers] -to [get_ports pLDE2] 15.625
set_max_delay -from [all_registers] -to [get_ports pLDMZE2] 15.625


#evaluate datapath only between different clock domains
#these are for the dirty_flag_24_bit, address and set are clocked in on 64MHz clock dirty flag is written on 128MHz
set_max_delay -from [all_registers] -to [get_cells U1/U71/U23/U2/DP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U71/U23/U2/SP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U71/U23/U3/DP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U71/U23/U3/SP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U71/U25/U2/DP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U71/U25/U2/SP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U71/U25/U3/DP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U71/U25/U3/SP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U72/U28/U2/DP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U72/U28/U2/SP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U72/U28/U3/DP] 7.813
set_max_delay -from [all_registers] -to [get_cells U1/U72/U28/U3/SP] 7.813

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Registered: ‎01-22-2015

Re: Reducing long net delay routing

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@dalepelletron

 

In the constraints file you wrote:

     #these generated clocks are created by counters/flip flops clocked by the 64 or 32MHz clocks

 

It seems that you are generating and routing some slow clocks in the FPGA fabric. This is not recommended as explained by avrumw in <this> post.  Be sure to read his description of the BUFGCE/BUFHCE method for creating slow clocks, which will keep routing of the clocks in the clock tree and help your design pass timing analysis.

 

Mark

 

 

Scholar drjohnsmith
Scholar
517 Views
Registered: ‎07-09-2009

Re: Reducing long net delay routing

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you are creating clocks divided by logic off the main clock,

 

This can be effectively thought of as asynchronous design, 

 

Use one clock, 

    generate off that 'pulses' one clock wide at the frequency you want, 

       and use those pulses to enable a register running at the full rate.

 

I'd suggest to start with also getting rid of the clock to out and clock to in constraints 

     concentrate on the clock structure first then the clock to out then the clock to in

           is how we teach here,

 

 

501 Views
Registered: ‎01-22-2015

Re: Reducing long net delay routing

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@dalepelletron

 

Be sure to consider drjohnsmith’s comment:

     generate off that 'pulses' one clock wide at the frequency you want,     

     and use those pulses to enable a register running at the full rate.

 

This is a great alternative to slow clocks (ie. clocks whose frequency is too low for generation by MMCM/PLL).

 

The following VHDL-snippets may help clarify drjohnsmith’s suggestion.

signal clk1, tog1 : std_logic;
.....
P1: process(clk1)
constant DIV1 : integer := 8; --divider for clk1
variable cnt : integer range 0 to DIV1-1;
begin
  if rising_edge(clk1) then
    if(cnt = 0) then
        tog1 <= '1';
        cnt := DIV1-1;
    else
        tog1 <= '0';
        cnt := cnt - 1;
    end if;
  end if;
end process P1;
--
P2: process(clk1)
begin
  if rising_edge(clk1) then
    if(tog1 = '1') then
         -- do something here....
    end if;
  end if;
end process P2;

 

Note how process, P1, creates a signal called tog1 (which some call a toggle) by dividing down clk1 (as you do).  The key point here is that tog1 is a signal and not a clock (ie. you don’t use constraints to define tog1 as a clock).  In process, P2, you can see how tog1 is used to make things happen at the rate of tog1 – even though the process is clocked at the rate of clk1.

 

There are other advantages of using toggles: 1) fewer constraints to write, 2) they free up the clock tree for other uses, and 3) they reduce the number of clock domains.  That is, tog1 is a signal in the clk1 clock domain.  So, you can pass signals from other processes clocked by clk1 into the process, P2, without using clock crossing circuits.

 

Mark

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