04-25-2016 12:34 PM
hi, i have a very simple design where i have a gated clock which drives a FF. i am implementing this design in ISE14p1 and targetting a V5 device.
the design is as follows
//inputs to design - clk1, clkg1, rst, din1
//outputs of design - dout1
assign clkg_out1 = clk1 & clkg1; //clkg_out1 is a wire
always @ (posedge clkg_out1 or negedge rst) begin
dout1 <= 4'd0;
dout1 <= din1 + 3'd5;
after implementation, the technology view looks correct (i see the clk1 is gated and clkg_out1 going into FF)
however what i observe is that when i try and constraint this design in the ISE constraints editor, clkg1 (which is the clock gate) shows up as an unconstrained clock, however i feel clkg_out1 (which is the output of the gated clock) should show up as the unconstrained clock.
1) why is clkg1 showing up as an unconstrained clock? and why not clkg_out1? is it a limitation of the tool, some setting i missed?
2) i cannot see clkg_out1 at all in the constraints editor. how do i constraint this gated clock output? esp because synthesis would have changed it's name. so how do i specify/constraint the clkg_out1 in my ucf?
gurus, please let me know ...
thansk and regards,
04-26-2016 03:09 AM
There might not be any TIME SPEC constraint defined in the ucf on clkg1, hence it shows up as an unconstrained clock.
clkg_out1 will not be shown in the constraint editor as a clock as it is an output of a LUT.(and gate).
You haveto manually write a time spec constraint for the clkg_out1 net w.r.t clk1 TS spec.
refer this AR38099 for more info on constraining gated clocks in ISE.
04-26-2016 12:53 PM
i have already defined a timespec constraint on clk1 as follows -
NET "clk1" TNM_NET = clk1;
TIMESPEC TS_clk1 = PERIOD "clk1" 10 ns HIGH 50%;
when i put the corresponding constraint on the clkg_out as -
INST "clkg_out11.O" TNM_NET = gated_clk;
TIMESPEC TS_gated_clk = PERIOD "clkg_out11.O" TS_clk1*1;
NET "clkg_out1" TNM_NET = gated_clk;
TIMESPEC TS_gated_clk = PERIOD "clkg_out1" TS_clk1*1;
for both of the above, i get the error in constraints editor as - cannot find TNM group for name for clkg_out11.O or clkg_out1 (where clkg_out11.O is the name of the clock gate net from the technology view, clkg_out1 is the net name from the RTL).
so how do i constraint the gated clock?
also, i've already looked at AR38099 and it's not useful. it tells the obvious - that we need to constraint a gated clock. however it does not tell how to do so, what constraint to put in manually or how to constraint it through the editor/locate a particular net via the constraint editor ...
so if anyone can shed more light on this, it would be great ...
04-27-2016 02:04 AM
clkg_out1 is derived from LUT which is a non-sequential element hence it will not be shown as unconstrained clock in constraint editor.
04-27-2016 12:12 PM
thanks for the inputs.
yes, i know we can use bufgce in place of such a clock gate which is LUT based. however in a typical FPGA device, we have about 16 - 32 bufgce available. in case i port ASIC RTL to FPGA, ASIC RTLs typically have ~ 50 clocg gates, maybe even more, hence using bufgce is not possible (they will fall short).
so now, since i dont have enough bufgces and ISE 14p1 does not support constraining a gated clock coming from a LUT, what other gated clock options do I have (in the tool) to either constraint or deal with gated clocks?
for 3rd party tools (like synplify), i know there are options like gated clock conversion. and once can also put constraint on LUT based clock outputs.
please let me know ...
04-28-2016 04:55 AM
I just googled and found that you had previously posted the similar query on forum long back which was answered by @avrumw,
Gating using any other resource, however, is a different story. If you try and gate a clock (say) using a LUT, then the clock needs to leave the clock network, be routed using general routing resources to a LUT, and then be routed back to something that can reach the desired clocks (probably another BUFG or BUFH). It is very difficult to ensure that the clock gated in a LUT is glitch free, and (more importantly) all the extra routing (including the extra BUFG/BUFH) will make this clock arrive later than any clock that stays on the clock tree. The amount of extra delay is variable from place&route run to place&route run, and is also process, voltage and temperature dependent. This kind of gating is NOT recommended in FPGAs.
The last point (which was made by another poster) is that each flip-flop within the FPGA has a CE pin. This prevents the updating of the data of the FF. In some cases, you can turn off the updating of some FFs when their value is not needed - this can be done automatically by the tools, and is called intelligent clock gating. By reducing the number of times a FF changes state unecessarily (and hence all the logic driven by that FF), the overall power of the system can also be reduced.
For Virtex 5 devices, the regional clock which can be used is BUFR. Please check out page number 40 in below clocking resources userguide:
05-03-2016 01:04 AM
I have your SR#10353972 which was filed on the same query with Xilinx technical support but all my emails to your hotmail ID are getting bounced back.
I have sent you a personal message in Xilinx forums. Please check and respond.
05-03-2016 10:04 PM
closing this thread as i have a duplicate thread in the "general technical discussions" forum ....