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Explorer
Explorer
751 Views
Registered: ‎05-22-2008

Register/Latch pins with no clock....

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My design meets timing and unless I mucked something up, works. However, where I run "check timing" I get:

1. checking no_clock
--------------------
 There are 20 register/latch pins with no clock driven by root clock pin: pl_eth_10g_i/dsp_pl/os_tuner_0/U0/axis_fft_rearrange_inst/packet_rearrange_inst/rs_sl_reg/Q (HIGH)

The relevant hdl is:

type addr_array is array (0 to 1) of std_logic_vector(15 downto 0);
signal raddr : addr_array;

signal rs_sl : std_logic;

--My hope is that this doesn't infer any HW?
function bit_to_uint( bit_input : std_logic ) return integer is
    variable slv : std_logic_vector(0 downto 0);
    begin
        slv(0) := bit_input;
        return to_integer(unsigned(slv));
    end;



.........

rw_proc: process(clk)
	begin
	if rising_edge(clk) then
        if rst = '0' then
            rd_addr <= bins;
            rs_sl <= '0';
        else
            ----------------------
            --- Read Side
            ----------------------
            read_selector_prev <= read_selector;

            if ((dout_rdy = '1') and (ram_state(read_selector) = FULL_BEING_EMPTIED ) )then
                
                if unsigned(rd_addr) = PKTLEN -1 then  -- Roll around
                    rd_addr <= (others=>'0');
                elsif unsigned(rd_addr) = unsigned(r_addr_last) then -- This is end-of-packet
                    rd_addr<= bins;
                    ram_state(read_selector) <= EMPTY_BEING_FILLED;
                    -- Switch Read RAMS
                    rs_sl <= not rs_sl;
                else
                    rd_addr <= std_logic_vector(unsigned(rd_addr) + 1 );
                end if;
            else
                null; --waiting for the current ROM to be ready to read
            end if;
        end if;
    end if;
end process;


--- convert sl '0' or '1' to integer 0 or 1
read_selector <= bit_to_uint(rs_sl);

raddr(read_selector) <= rd_addr;

Note that read_selector is utilized elsewhere in the design. When I look at the schematic, it appears that LDCEs are being placed on the address line to my RAMs ( RAM not shown in the above HDL). I questioned if this logic was going to work, and I'm certain I can use a couple of WHEN/ELSE statements, but I would like to further understand what is happening behind the scenes.

First and foremost, rs_sl isn't a clock, at least I don't intend it to be one, so why are the tools picking it upas such?

Second, the 20 pins it's talking about, raddr_reg are LDCE's that it has inferred, and it's inferring a set for each of the 2 raddr's. 

In looking back at it now, I don't think I ready need the "raddr(read_selector) <= rd_addr" logic, which i'm sure is the problem, but I was trying to be consistent, in terms of switching all my signals, and not driving nonzero addresses to ram that aren't being read, despite the existence of an enable pin on the ram.

Can anyone speak to what the synthesizer/router/placer does on something like "raddr(read_selector) <= rd_addr"? I know it's sketchy coding.

 

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Xilinx Employee
Xilinx Employee
524 Views
Registered: ‎05-14-2008

Re: Register/Latch pins with no clock....

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@mckinjo4 

Yes, the latch is inferred from this line:

raddr(read_selector) <= rd_addr;

This line implies that when read_selector=0, raddr(0) <= rd_addr but  raddr(1) keeps unchanged; And when read_selector=1, raddr(1) <= rd_addr but  raddr(0) keeps unchanged. So the "keeping unchanged" logic is implemented with latches.

I don't think you want logics like this. What is the actual connection between raddr and rd_addr?

-vivian

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6 Replies
Explorer
Explorer
569 Views
Registered: ‎01-15-2019

Re: Register/Latch pins with no clock....

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Any response? I have the same problem ...

 

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Scholar drjohnsmith
Scholar
562 Views
Registered: ‎07-09-2009

Re: Register/Latch pins with no clock....

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Try simulating the design ,

 

out of interest under reset, what does ram_state(read_selector) get set to ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar drjohnsmith
Scholar
558 Views
Registered: ‎07-09-2009

Re: Register/Latch pins with no clock....

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re the type converoisn functoin

 

is this of any use ?  It lives in the front of my log book always.

 

http://www.bitweenie.com/listings/vhdl-type-conversion/

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
530 Views
Registered: ‎05-14-2008

Re: Register/Latch pins with no clock....

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@ldm.eth 

Your design has unexpected latch or you have latch clock pins with no_clock defined?

Please start a new thread for your own question if you don't find answer in the forums.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
525 Views
Registered: ‎05-14-2008

Re: Register/Latch pins with no clock....

Jump to solution

@mckinjo4 

Yes, the latch is inferred from this line:

raddr(read_selector) <= rd_addr;

This line implies that when read_selector=0, raddr(0) <= rd_addr but  raddr(1) keeps unchanged; And when read_selector=1, raddr(1) <= rd_addr but  raddr(0) keeps unchanged. So the "keeping unchanged" logic is implemented with latches.

I don't think you want logics like this. What is the actual connection between raddr and rd_addr?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Explorer
Explorer
505 Views
Registered: ‎05-22-2008

Re: Register/Latch pins with no clock....

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@viviany 

So, I'm just demuxing address lines that are connected as address inputs to sveral RAMs. I almost certainly don't need to demux them; in a textbook implementation, they would just be fanned out, and a read_enable and/or chip_enable would be used. I don't remember now, but I probably was demuxing in this manner to make debug and visualization of the pipelining and switching easier. 

 

Thank you for your answer though. It's often hard to find information about how seemingly concurrent assignments (...<=... outside of a process), with a non-static left hand side get implemented. 

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