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Registered: ‎03-22-2021

Report unconstrained input and output delay


In my design some of my inputs and outputs delays will not be constrained, i was wondering if after the implementation step can i report the inputs and outputs delay introduced for those outputs and inputs by the tool?

More specifically will the tool report the delay between my port INPUT1 and the first flop that registers that input?

Same thing for outputs.

Is there a tcl command to do that?

Thank you

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2 Replies
Registered: ‎01-23-2009

Let me split this question in two.

As for the second part - is there a command that generates required setup/hold for inputs and min/max clock to output for outputs, the answer is "yes" - report_datasheet, which is also available from the GUI using Reports -> Timing -> Report Datasheet.

But what I want to be clear about is that this does NOT replace having input and output constraints. Even if you do a report_datasheet, this merely gives you the timing of this specific implementation run; there is nothing that states that this will be the same in any future implementation run; yes - there are things that you can do that minimize this variation (used dedicated clocking resources, have all your IOs use IOB flip-flops)... But, all inputs and outputs should be constrained - even if all your I/Os use IOB flops. You should then count on the timing determined by your constraints - not by the timing of a given implementation as reported by the report_datasheet.


Registered: ‎03-22-2021

Thanks for your help,

The timings of some interfaces of the FPGA are not specified that is why i do not constrain these IO.

Furthermore i'm having some difficulties understanding the set_input_delay and set_ouput_delay command.

Let's say i have an input I1 and a flip flop reg1 that registers that input 

If i want a maximum delay of 5 ns between that input and that flop should i use a set_input_delay max of 5ns and set_input_delay min of 0 ns?

Sometime i see a set_input_delay of -10 ns ( a negative value) and that confuses me because i don't understand how a delay can be negative

The calculation and concept of Rise Max and Rise Min in the constraint wizard confuses me

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