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475 Views
Registered: ‎02-17-2020

Requesting help to overcome timing errors: [Timing 38-282] The design failed to meet the timing requirements

Hi,

I need help in closing this timing error 38-282 that shows up after the implementation step.

Details:

Evaluation board: Zybo z7020
Clocking wizard: 100 MHz sys clock (pin K17) to generate 104MHz clock which is supplied to XADC and xfft_0 DSP blocks.
{set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports sysclk];
create_clock -add -name sys_clk_pin -period 10.00 -waveform { 0 5 } [get_ports sysclk]; }

Timing report:Timing summaryTiming summary

Failing paths:

2.pngZoomed In failing zoneZoomed In failing zone

Attached: Timing report summary

I tried Flow_runPhyOpt implementation strategy but the error still persists. Please help me in overcoming this error. 

Thanks!

 

 

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3 Replies
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Adventurer
Adventurer
408 Views
Registered: ‎05-30-2017

Hi,

I recommend you start with this video: https://www.xilinx.com/video/hardware/timing-closure.html

Timing closure, in general, is not a simple issue that can likely be solved via the Xilinx forum. It is one of the fundamental skills that must be developed over time by an FPGA engineer. If you just need it to work right now, and don't have time for all of that, I recommend dropping your "clock wizard clock_out1 " by half.
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396 Views
Registered: ‎02-17-2020

Thanks for the response, Mr. Ryan! I would try to figure out the timing closure methods as per your recommendation. Yes, operating on lower clock frequencies seems to not give this timing error. I would check the maximum frequency I can operate on without errors.

I would like to understand what would be the effects of using a bit stream file generated from a project with timing errors such as 38-282. In some cases, I observed that the bit file being generated even though there the timing errors that are not brought to a closure. In such a case, what faults can I expect from the hardware implementation?
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Moderator
Moderator
371 Views
Registered: ‎11-04-2010

Hi, bhaskara@tamu.edu ,

The bit file can still be generated without timing closure being achieved.

In this situation, Vivado cannot promise the correctness of hardware function. It may be incorrect or correct. 

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