UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
614 Views
Registered: ‎01-02-2012

Rough estimation of the individual 'P', 'V' & 'T' variations

Jump to solution

Hello experts,

Designing for a -1L grade industrial Artix-7 device, most of the IO-delays I observe/measure are very close to the FAST corner case and they do not vary much with temperature. 

Hence my question: A path-delay is estimated to vary from 2 to 7 ns regarding all PVT-factors by STA.
How much do  'P', 'V' & 'T' individually contribute to this 5 ns total variation? i.e. what would be the variation, if the core voltage (0.95V) is perfectly stable and/or the temperature is fixed? 

Regards & have a nice weekend!

0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
456 Views
Registered: ‎07-18-2018

Re: Rough estimation of the individual 'P', 'V' & 'T' variations

Jump to solution

most of the IO-delays I observe/measure are very close to the FAST corner case and they do not vary much with temperature.

If you are willing to characterize each device for your design, you might be able to find that it happens to be a FAST device under your conditions and it might work perfectly fine. But the next device might not work exactly the same and you would need to repeat the process of self characterizing.

The PVT for static timing is provided such that any part that meets that speed and temp grade, will work on any part, with any combination of Voltage and Temp, with whatever design the user might have implemented. It's intrinsically conservative as no device can be both corners, at two different voltages and temperature extremes at the same time.

It use to be for 5 Series and before you could pro-rate the devices. And get some of that margin back, but because the FAST and SLOW corner are not simply the extremes of temp and voltage, at some point around 65nm devices it seems the variation of VT across process was larger then the improvement from restricted temperature/voltage per the below AR. So when you used the pro rated numbers, it didn't give you any additional margin.

https://www.xilinx.com/support/answers/32216.html

 

Tags (1)
4 Replies
570 Views
Registered: ‎01-08-2012

Re: Rough estimation of the individual 'P', 'V' & 'T' variations

Jump to solution

'P' can vary quite a bit.  Consider that the various speed grades are (at least for early production runs) "binned" i.e. they make a bunch of chips, test them, and the fast ones go in the -3 bin, the slow ones go in the -1 bin, etc.

You are using a 7 series part which has been in production for several years.  For a mature process like that, one would expect that there's a good chance that your -1 part is actually fast enough to be a -2 or even -3.  This seems consistent with your measurements.  But you can't count on it!  You really must follow the worst case datasheet figures because there is a chance that you will get a part that's only fast enough to just scrape in to the -1 bin.  In general, this chance gets lower as the process matures, but it will never be zero.

You have a -1L (rather than -1) part.  I don't know whether these are a special build, or whether they're just selected for lower current.  The above comments still apply though.

(There's also the chance that TSMC let the intern loose with the ion implanter and there's a whole batch of chips that are slower ;-)

0 Kudos
Historian
Historian
543 Views
Registered: ‎01-23-2009

Re: Rough estimation of the individual 'P', 'V' & 'T' variations

Jump to solution

The short answer is that all three variables matter - all three of them are in the same order of magnitude. If anything, Voltage is the lesser of the three...

But the bigger question is "what do you plan to do with this information". The variation reported by static timing is the only thing you can count on. If you design a system that does not allow for the complete variation, then, by definition, you have an unreliable system - you can do whatever analysis or measurement you want, but in the end, nothing other than the full MIN to MAX variation is guaranteed by Xilinx - even if you restrict the operating conditions of the FPGA.

If your system cannot tolerate the full variation, then maybe you can tell us what you are trying to do - there are mechanisms of designing FPGA systems that can reduce some of this variation using the MMCMs and PLLs properly...

Avrum

0 Kudos
Explorer
Explorer
457 Views
Registered: ‎07-18-2018

Re: Rough estimation of the individual 'P', 'V' & 'T' variations

Jump to solution

most of the IO-delays I observe/measure are very close to the FAST corner case and they do not vary much with temperature.

If you are willing to characterize each device for your design, you might be able to find that it happens to be a FAST device under your conditions and it might work perfectly fine. But the next device might not work exactly the same and you would need to repeat the process of self characterizing.

The PVT for static timing is provided such that any part that meets that speed and temp grade, will work on any part, with any combination of Voltage and Temp, with whatever design the user might have implemented. It's intrinsically conservative as no device can be both corners, at two different voltages and temperature extremes at the same time.

It use to be for 5 Series and before you could pro-rate the devices. And get some of that margin back, but because the FAST and SLOW corner are not simply the extremes of temp and voltage, at some point around 65nm devices it seems the variation of VT across process was larger then the improvement from restricted temperature/voltage per the below AR. So when you used the pro rated numbers, it didn't give you any additional margin.

https://www.xilinx.com/support/answers/32216.html

 

Tags (1)
Explorer
Explorer
439 Views
Registered: ‎01-02-2012

Re: Rough estimation of the individual 'P', 'V' & 'T' variations

Jump to solution

Hi @evant_nq,

thanks for the great AR link: If this is still valid, 'T' is really much less relevant compared to 'V' & 'P'.
Thank you all ( @avrumw@allanherriman ) for the answers. I am just trying to understand the silicon, to become a better engineer. I know that, in the end only the STA results matter.

@avrumw, I could solve this issue by ditching the IDDRs and using internal routing in order to compensate the long/variable clock delay. 

 

  

0 Kudos