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Registered: ‎08-11-2017

SLL net delay in UltraScale+

I would like to know the SLL net delay on my device (xcvu7p-flvb2104-2-e), unfortunately the Path Report only gives the whole routing cost, not differentiating the net delays up to the SLL entry point, exit point or the SLL delay itself.


Fixed placement and routing with FFs closest to the border between SLRs:





Fixed placement and routing with FFs in the middle of the clock region (bottom clock region of the top SLR, top clock region of the bottom SLR):





Estimated net delay between border and middle of the clock region (no SLR crossing):





Do you agree with the following conclusions?


  • SLL delay is reduced by about 400ps (total delay = 1.2ns) if FFs are placed on the middle of clock region;
  • The extra 400ps delay is the routing cost between the border FF and the middle of the clock region;
  • SLLs are located in the middle of the clock region, and their cost is about 1.2ns

Is there any documentation or speed file which clearly states the SLL net delay? I have not seen anything about that in the UltraFast Design Methodology.

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Registered: ‎04-18-2011

Why do you expect it to report the net in this way?

(The tools understand all the net delays. splittling them up like this would only mean adding them back up later on to compute the setup and hold slacks)

I am not sure your test tells you much. it is letting the tools pick the route between two locked FF's. 

In fact the flops placed close to the boundary seems to have the larger net delay compared to the case where the flops are placed further apart. it looks like there is a small Jog in that net compared to the second test. Possibly trying to fix up some hold time error... 


Without trying to be blunt, you either need to cross the SLR boundary or you don't.

If you do there is a description of the best practices for doing this in UFDM. 


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