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Newbie jross001
Newbie
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Registered: ‎11-01-2018

SRIO V5.6 V5Q Fails Timing

Hello, I'm having trouble with closing timing using the example desing of a 4x 3.125Gbps SRIO core targeting the V5Q (XQR5VFX130-CF1752-1).  It fails timing on UCLK 6.4ns TIMEGRP.  All timing failures occur in the LOG, BUF, and PHY cores which are netlists, so no editing possible.

I've generated the core for a standard V5 part (XC5VFX130T-FF1738-1) and when I built the example design on it, I had no timing violations.  Simply targeting the V5Q part and re-running PAR, I get a ton of timing errors.  Was wondering if anyone else ran into this or what types of things could be done to mitigate the issue.

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