09-11-2019 02:59 AM - edited 09-11-2019 03:03 AM
I'm trying to make stable output clocks from MMCM as below figure (my FPGA is Kintex UltraScale+ and I'm using Vivado 2018.2).
Although there might be some phase difference (phase alignment is necessary) between 2 output clocks, they have same frequency.
My question is if I check the 'Safe Clock Startup' as below figure, will the clock outputs behave as case 1 or case 2?
# case 1
The time when clock is stable is different as below figure.
the 'Safe Clock Startup' feature applies to the outputs respectively (or independently).
That is, if one clock is stable, it activates regardless of the state (stable of unstable) of the other clock as above figure.
In the above figure, clk0 activates when it is stable; it doesn't care if clk1 is stable or not.
And after clk1 is stable, it activates then.
# case 2
The time when clock is stable is different, similar to case 1.
In this case, clock outputs activates when all of the clocks are stable.
In the above figure, clk0 is stable earlier than clk1 but it delays its' activation until clk1 is also stable.
As a result, every clock outputs activates at the same time.
Which scenario is correct? Case 1 or Case 2?
Thank you for your help.
09-11-2019 03:10 AM
09-17-2019 01:47 PM
I suspect you are looking at the MMCM “Safe Clock Startup and Sequencing” as a way to startup some modules of your design before others.
Another method of doing this is to not use “Safe Clock Startup and Sequencing” and instead create a power-on reset for your design from the “locked” output of the MMCM. The power-on reset feeds a circuit called a reset-bridge (aka async reset synchronizer). The output of the reset-bridge is then used to bring a module (clock-domain) of your design out of reset. It is possible to cascade reset-bridges so that some modules (clock-domains) of your design come out of reset before other modules.