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Adventurer
Adventurer
87 Views
Registered: ‎11-18-2017

'Safe Clock Startup' feature in a MMCM

 

Hello.

 

I'm trying to make stable output clocks from MMCM as below figure (my FPGA is Kintex UltraScale+ and I'm using Vivado 2018.2).

cs1.JPG

 

Although there might be some phase difference (phase alignment is necessary) between 2 output clocks, they have same frequency.

My question is if I check the 'Safe Clock Startup' as below figure, will the clock outputs behave as case 1 or case 2?

cs4.JPG

 

# case 1

The time when clock is stable is different as below figure.

cs2.JPG

 

the 'Safe Clock Startup' feature applies to the outputs respectively (or independently).

That is, if one clock is stable, it activates regardless of the state (stable of unstable) of the other clock as above figure.

In the above figure, clk0 activates when it is stable; it doesn't care if clk1 is stable or not.

And after clk1 is stable, it activates then. 

 

 

# case 2

The time when clock is stable is different, similar to case 1.

cs3.JPG

 

In this case, clock outputs activates when all of the clocks are stable.

In the above figure, clk0 is stable earlier than clk1 but it delays its' activation until clk1 is also stable.

As a result, every clock outputs activates at the same time.

 

Which scenario is correct? Case 1 or Case 2?

 

Thank you for your help.

 

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2 Replies
Xilinx Employee
Xilinx Employee
81 Views
Registered: ‎05-22-2018

Re: 'Safe Clock Startup' feature in a MMCM

Hi @kimjaewon ,

I think it depends if Sequencing is true or not:

savegaurdCapture.JPG

Reference link:

https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf

Thanks,

Raj

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17 Views
Registered: ‎01-22-2015

Re: 'Safe Clock Startup' feature in a MMCM

@kimjaewon 

I suspect you are looking at the MMCM “Safe Clock Startup and Sequencing” as a way to startup some modules of your design before others. 

Another method of doing this is to not use “Safe Clock Startup and Sequencing” and instead create a power-on reset for your design from the “locked” output of the MMCM.  The power-on reset feeds a circuit called a reset-bridge (aka async reset synchronizer).  The output of the reset-bridge is then used to bring a module (clock-domain) of your design out of reset.  It is possible to cascade reset-bridges so that some modules (clock-domains) of your design come out of reset before other modules. 

You will find VHDL that describes the reset-bridge <here> and a lengthy thread that discusses resets <here>.

Mark

 

 

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