11-06-2017 05:40 PM - edited 11-06-2017 07:08 PM
I'm using VIVADO 2016.1 and newbie to this tool.
I synthesized and implemented device using 144 MHz clock(from outside) and wanted to pass timing but there was.
I checked synthesis & implement options(such as retiming, directive(explore)), but it did not pass.
How can I solve this problem?
Do I have to deal with IBUF, IBUFG, etc.?
11-06-2017 07:13 PM
Too many logic levels between the two RAMB36E1 cells and the destination is the enable signal of the BRAM.
You can try to reduce the logic levels and consider adding a level of register so that the BRAM enable pin is driven by a register directly.
I suggest you read UG949 in which it gives general methodology of timing error analysis and solutions.
11-06-2017 08:18 PM - edited 11-06-2017 09:30 PM
I think I cannot modify microblaze block nor microblaze_0_local_momery.
I can only consider the path between two block, am I right?
In this case, can I reduce logic levels?
Also, I want to know the "destination", enable signal of the BRAM. Can you explain the pin name of enable signal of the BRAM?
I want to know about 2nd solution in detail.
11-07-2017 07:37 PM
The destination pin of this path can be seen in the timing report snapshot you posted:
I just noticed that the object names on this path are almost in Xilinx IP. You're not supposed to modify the source files in Xilinx IP. You can only modify the user source files.
If all the corresponding source files for this path are all in Xilinx IP, it is not possible for you to reduce the logic level unless the IP provides options that can generate less logic levels.
In this case, my suggest for you is to try different Implementation strategies. You can try 5~6 strategies at the same time.