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Visitor
Visitor
8,221 Views
Registered: ‎11-08-2015

Setup Timing Violation

I have a design which violates setup timing. The output from the timing report is at the bottom. 

But the path listed here is a user input path, which we don't care about the delay value. I wonder if there is a way I can let the timing analysis ignore this particular path. Can someone let me know what lines are to be added to the constraint file. Thanks!!

 

Max Delay Paths
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Slack (VIOLATED) : -0.063ns (required time - arrival time)
Source: MY_DF_MAIN/IDOOUT_FRAME_WEN_MONITOR_reg/C
(rising edge-triggered cell FDRE clocked by main_clk_i {rise@0.000ns fall@3.333ns period=6.667ns})
Destination: MY_DF_MAIN/INST_OUTPUT_DATA_OPERATOR.my_output_data_operator/OUTPUT_SLINK_OUT[27].SLINK_PACKER/INST_SHORT_FRAME_FIFO.FRAME_INPUT_FIFO/WriteAddress/BinaryCount_reg[0]/CE
(rising edge-triggered cell FDPE clocked by main_clk_i {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: main_clk_i
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.667ns (main_clk_i rise@6.667ns - main_clk_i rise@0.000ns)
Data Path Delay: 6.453ns (logic 0.223ns (3.456%) route 6.230ns (96.544%))
Logic Levels: 0
Clock Path Skew: -0.017ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.861ns = ( 9.528 - 6.667 )
Source Clock Delay (SCD): 3.016ns
Clock Pessimism Removal (CPR): 0.138ns

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Xilinx Employee
Xilinx Employee
8,212 Views
Registered: ‎05-07-2015

HI @zihaoj


I am not sure whether this path qualifies to be ignored. But If you are sure aboutit,

You can use set_false_path constraint to ignore this specific path.
Refer tcl command reference guide UG835 for usage.
page 1237.
If you are not familiar with xdc constraints , the best way to  do it would be to right click on the path you are certain about ignoring and click on set_false_path. (choose from start point to end point option).

Thanks
Bharath
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Xilinx Employee
Xilinx Employee
8,206 Views
Registered: ‎09-20-2012

Hi @zihaoj

 

If you are using ISE then refer to page-31 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf

Thanks,
Deepika.
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Moderator
Moderator
8,186 Views
Registered: ‎07-01-2015

Hi @zihaoj,

 

You can add timing ignore constraint to ucf if you are using ISE

TIMESPEC "<name of spec>" = FROM "<source>" TO "<destination>" TIG;

 

If you are using Vivado please add set_false_path constraint in XDC. As you want to apply for single path you can use 

set_false_path -from <source> -to <destination>

 

Thanks,
Arpan

Thanks,
Arpan
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