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raksssss
Adventurer
Adventurer
360 Views
Registered: ‎09-04-2019

Setup Timing violation

Hi,

I would like to know about few setup violations that I observe in the designs. 

1.  1 bit control signals which comes which are required in two clock domains(CDC) for some operation, have likely setup violations between first/second flop. Is it safe to set these paths as false paths? or How to handle these paths if violation comes?

Ex  : set_false_path -from [get_pins i_txcontroller/rd_done_reg/C] -to [get_pins i_seb_txcontroller/w_buf2_rd_done_d_reg/D]

(rd_done is one clock domain, rd_done_d is the delayed version on another clock domain)

2. Setup violations observed on ILA paths. Does it going to affect anything on onboard ILA observations and Is it safe to ignore these in the design or is it anyway critical?

Thanks in advance

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2 Replies
viviany
Xilinx Employee
Xilinx Employee
334 Views
Registered: ‎05-14-2008

1. It depends. You need to analyze why this path fails timing, the relationship between the two clock domains, sync or async, frequency and phase relationship...

False path means no matter how the tool place and route this path, the data can definitely correctly captured at the destination register, or even a wrong data is captured it does not harm the design function. So it is the designer to determine if your path is safe to ignore.

2. The timing violations in ILA paths need to be fixed. Those violations could cause the ILA capturing wrong data.

-vivian

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avrumw
Expert
Expert
268 Views
Registered: ‎01-23-2009

If you are bringing a signal from one clock domain to another clock domain, you must have a clock domain crossing circuit (CDCC). Part of a proper CDCC is a timing exception on the actual clock domain crossing path.

Depending on the CDCC the proper exception might be a false path, or might be a set_max_delay -datapath_only constraint.

For a slow changing single bit signal, the CDCC can be as simple as a simple metastability reduction circuit - two back to back flip-flops on the destination clock domain with the ASYNC_REG property set on both. For this kind of CDCC there are no specific requirements for the clock domain crossing path itself - it would be legal from the CDCC's point of view to have a set_false_path from the last flip-flop in the source domain to the first flip-flop in the destination domain (which is the first flip-flop of the metastability reduction circuit). This path must be directly flip-flop to flip-flop - you cannot have combinatorial logic on it for a legal CDCC.

However, putting a set_false_path on it theoretically makes the latency through the CDCC unbounded - the route from the last FF on the source clock domain to the first FF on the destination clock domain will have no constraint and therefore can theoretically be arbitrarily long. In most cases, it is desirable to bound this delay from a system point of view - you want your destination domain to react to a change in this signal within some finite and bounded time. To do this you use a set_max_delay -datapath_only on the path; for the value, put whatever you think is reasonable - this will be the bound on the latency. It is traditional to use the period of one or the other or the faster of the two clocks...

Avrum