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Observer kirito0816
Observer
387 Views
Registered: ‎11-26-2018

Setup time violation between reset and DDR4 port

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Hello,

I met a problem after I finish the implementation of an AXI design using Vivado 2016.4. There is a setup time violation between reset and ddr4. 11.PNG22.PNG33.PNG44.PNG55.PNG

I find out there is a big "net delay" caused by big fanout. So I tried to reduce the fanout of signal "func_rst_n". I tried "max_fanout" and copying "BUFG" but it does not work. Could you please give some advice? Thank you.

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1 Solution

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Xilinx Employee
Xilinx Employee
315 Views
Registered: ‎05-14-2008

Re: Setup time violation between reset and DDR4 port

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You're connecting a reset signal generated by a 50MHz clock to the DDR4 IP which is working at 250MHz.

The DDR4 IP is synchronizing the reset signal to the 250MHz clock domain.

The BUFG on the reset net increases the path delay and it fails to meet the 4ns requirement.

You can have the "func_rst_n_reg" duplicated and have one of them fed into the DDR4 IP without BUFG.

-vivian

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Xilinx Employee
Xilinx Employee
360 Views
Registered: ‎02-27-2019

回复: Setup time violation between reset and DDR4 port

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Hi @kirito0816 ,

Could you insert a register between two FDREs instead of BUFG , then report the timing to have a look?

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Xilinx Employee
Xilinx Employee
353 Views
Registered: ‎05-14-2008

Re: Setup time violation between reset and DDR4 port

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Can you show us the detailed path analysis of this path?

The setup requirement of the failing path is 4ns while the other paths between the same two clock domains have a requirement of 20ns.

Would like to know the clock frequencies and the relationship between the two clocks.

When you double click on the row highlighted in below image, the path details window will be opened.

-vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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path details.png
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Observer kirito0816
Observer
341 Views
Registered: ‎11-26-2018

回复: Setup time violation between reset and DDR4 port

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Thank you. I will try it and give you the result.

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Observer kirito0816
Observer
337 Views
Registered: ‎11-26-2018

Re: Setup time violation between reset and DDR4 port

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The ratio of two clk is 5:1. And here is the detail. 66.PNG77.PNG88.PNG

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Xilinx Employee
Xilinx Employee
316 Views
Registered: ‎05-14-2008

Re: Setup time violation between reset and DDR4 port

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You're connecting a reset signal generated by a 50MHz clock to the DDR4 IP which is working at 250MHz.

The DDR4 IP is synchronizing the reset signal to the 250MHz clock domain.

The BUFG on the reset net increases the path delay and it fails to meet the 4ns requirement.

You can have the "func_rst_n_reg" duplicated and have one of them fed into the DDR4 IP without BUFG.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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Observer kirito0816
Observer
304 Views
Registered: ‎11-26-2018

Re: Setup time violation between reset and DDR4 port

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Thank you very much. This is the process to get "func_rst_n". Do I need to copy the process and use a "250mhz clk" for it? 99.PNG

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