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Registered: ‎06-28-2017

Setup time violation on reset using vivado 16.3 with zynq (multicyle vs false path)

Simple so I have  Vivado 16.3 with ZYNQ embedded design and I am getting setup violations for my reset net. The setup  violations are within one of my AXI peripherals and specifically on the reset net that goes to several xilinx cores (fifo, bram, etc) that use an async reset (im not sure if a sync reset even exists for these cores, it is a also a pain to regenerate everything even if they did). My question is does it really matter.... my block design uses a master reset controller for the PL in the form of a "Processor System Reset Module (PG164)"  since my violation is on a few xilinx cores within a peripheral and all my axi peripheral's resets come from the  "Processor System Reset Module" which supposedly has a acync reset output signal that is asserted (held in 'reset') for 16 clock cycles - when a the system is in 'reset'. Does it really matter that im getting setup violations when the reset line in question is going to be in the 'reset' state for 16 clocks.... i tried setting the violations them as multicycle path but it just made timing worse. im not sure if i should just simply mark this as a false path or not. Or just simply ignore the violations.  Whats the best course of action?

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3 Replies
Registered: ‎01-16-2013



Can you please provide the timing report to analyze the path and provide the suggestions?



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Registered: ‎06-28-2017


Path Group: **async_default**
From Clock: clk_fpga_0
To Clock: clk0_design_1_clk_wiz_0_0

Setup : 1 Failing Endpoint , Worst Slack -0.051ns, Total Violation -0.051ns
Hold : 0 Failing Endpoints, Worst Slack 0.519ns, Total Violation 0.000ns

Max Delay Paths
Slack (VIOLATED) : -0.051ns (required time - arrival time)
Source: design_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: design_1_i/ModBridge_0/inst/DualTrans_1/Fifo_LeftDec/FIFO_DUALCLOCK_MACRO_inst/bl.fifo_18_inst_bl.fifo_18_bl/RST
(recovery check against rising-edge clock clk0_design_1_clk_wiz_0_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: **async_default**
Path Type: Recovery (Max at Slow Process Corner)
Requirement: 5.000ns (clk0_design_1_clk_wiz_0_0 rise@5.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 2.235ns (logic 0.456ns (20.407%) route 1.779ns (79.593%))
Logic Levels: 0
Clock Path Skew: -0.183ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.843ns = ( 7.843 - 5.000 )
Source Clock Delay (SCD): 3.026ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.265ns ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.128ns
Phase Error (PE): 0.099ns
Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
net (fo=1, routed) 1.193 1.193 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
net (fo=4273, routed) 1.732 3.026 design_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
SLICE_X61Y49 FDRE r design_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X61Y49 FDRE (Prop_fdre_C_Q) 0.456 3.482 r design_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
net (fo=128, routed) 1.779 5.261 design_1_i/ModBridge_0/inst/DualTrans_1/Fifo_LeftDec/FIFO_DUALCLOCK_MACRO_inst/lopt
RAMB18_X5Y18 FIFO18E1 f design_1_i/ModBridge_0/inst/DualTrans_1/Fifo_LeftDec/FIFO_DUALCLOCK_MACRO_inst/bl.fifo_18_inst_bl.fifo_18_bl/RST (IS_INVERTED)
------------------------------------------------------------------- -------------------

(clock clk0_design_1_clk_wiz_0_0 rise edge)
5.000 5.000 r
PS7_X0Y0 PS7 0.000 5.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[1]
net (fo=1, routed) 1.088 6.088 design_1_i/clk_wiz_0/inst/clk_in1
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 6.179 r design_1_i/clk_wiz_0/inst/clkin1_bufg/O
net (fo=1, routed) 1.612 7.792 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0
-3.425 4.366 r design_1_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 1.725 6.091 design_1_i/clk_wiz_0/inst/clk0_design_1_clk_wiz_0_0
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 6.182 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
net (fo=2586, routed) 1.661 7.843 design_1_i/ModBridge_0/inst/DualTrans_1/Fifo_LeftDec/FIFO_DUALCLOCK_MACRO_inst/TxRxClock0
RAMB18_X5Y18 FIFO18E1 r design_1_i/ModBridge_0/inst/DualTrans_1/Fifo_LeftDec/FIFO_DUALCLOCK_MACRO_inst/bl.fifo_18_inst_bl.fifo_18_bl/RDCLK
clock pessimism 0.000 7.843
clock uncertainty -0.265 7.577
RAMB18_X5Y18 FIFO18E1 (Recov_fifo18e1_RDCLK_RST)
-2.368 5.209 design_1_i/ModBridge_0/inst/DualTrans_1/Fifo_LeftDec/FIFO_DUALCLOCK_MACRO_inst/bl.fifo_18_inst_bl.fifo_18_bl
required time 5.209
arrival time -5.261
slack -0.051




the "peripheral_aresetn_reg" comes from Xilinx    (design_1_rst_ps7_0_50M_0)  "Processor System Reset 5.0" which according to datasheets when a reset event occurs the output pins to the peripherals are asserted and stay in reset  for 16 clock cycles.


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Registered: ‎06-28-2017

Attached full timing report in zip file...

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