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inst_npn

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07-17-2017 03:18 AM

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Registered:
06-30-2017

Hello users,

I understand the setup time is defined before active clock edge and hold time is defined after active clock edge.

What is the significance of positive and negative values for set_output_delay -max/min ???

Please correct me if I am wrong. Per my understanding, A negative value of set_output_delay -max, for example,

set_output_delay -clock CLK -max -1.0

means Tsetup is defined after clock edge. Similarly for -min value, negative value of Thold

set_output_delay -clock CLK -min -1.0

is defined before clock edge. Am I correct???

What about the significance of Tsetup + Thold should always be positive in this case(-2)?

Are the above constraints wrong??

Thanks. Your time is appreciated.

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avrumw

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07-17-2017 07:25 AM

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Registered:
01-23-2009

set_output_delay -clock CLK -max -1.0

means Tsetup is defined after clock edge.

Yes. The set_output_delay -max is the value of the setup time (tSU) - so this means a tSU=-1, so the required data valid window starts 1ns after the edge of the clock.

set_output_delay -clock CLK -min -1.0

is defined before clock edge. Am I correct???

No. For the set_output_delay, the -min is the **negative** of the hold requirement. Thus, this constraint means that the hold time requirement (tH) is 1ns; 1ns after the edge of the clock.

What about the significance of Tsetup + Thold should always be positive in this case(-2)?

So actually, in this case Tsu + Th = 0, not -2.

Are the above constraints wrong??

Yes.

Let's take a couple of examples...

First, the typical one - If the required data valid window (from the downstream device) starts at -1ns (1ns before the clock edge) and ends at 2ns (2ns after the clock edge), then this has a tSU=1 and tH=2 - both positive and a total required data window of 3ns.

Now lets assume a late required data valid window - it starts at 1ns after the clock and ends 4ns after the clock - still 3ns, but in this case the tSU=-1 and tH=4.

Similarly an early required data valid window - it starts at t=-4 and ends at t=-1 - again still 3ns. This would be tSU=4, tH=-1.

All of these have a 3ns required data valid window, which means that tSU + tH = 3ns. Remember that for the set_output_delay, the -max is the required setup time and the -min is the negative of the required hold time. So for our 3 cases we would have

a) max=1, min = -2

b) max= -1, min = -4

c) max =4, min = 1

In all three of these cases, the min is smaller than the max, which is required (and makes sense - how can a min be greater than a max)

Now yours; your max = -1 (tSU=-1) and your min = -1 (tH = 1). This means that the required window starts 1ns after the edge of the clock and ends 1ns after the edge of the clock. This means that the device doesn't actually need a valid data window (well, it needs an instantaneous one). No real device can have this kind of characteristic.

Avrum

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avrumw

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07-17-2017 07:25 AM

13,083 Views

Registered:
01-23-2009

set_output_delay -clock CLK -max -1.0

means Tsetup is defined after clock edge.

Yes. The set_output_delay -max is the value of the setup time (tSU) - so this means a tSU=-1, so the required data valid window starts 1ns after the edge of the clock.

set_output_delay -clock CLK -min -1.0

is defined before clock edge. Am I correct???

No. For the set_output_delay, the -min is the **negative** of the hold requirement. Thus, this constraint means that the hold time requirement (tH) is 1ns; 1ns after the edge of the clock.

What about the significance of Tsetup + Thold should always be positive in this case(-2)?

So actually, in this case Tsu + Th = 0, not -2.

Are the above constraints wrong??

Yes.

Let's take a couple of examples...

First, the typical one - If the required data valid window (from the downstream device) starts at -1ns (1ns before the clock edge) and ends at 2ns (2ns after the clock edge), then this has a tSU=1 and tH=2 - both positive and a total required data window of 3ns.

Now lets assume a late required data valid window - it starts at 1ns after the clock and ends 4ns after the clock - still 3ns, but in this case the tSU=-1 and tH=4.

Similarly an early required data valid window - it starts at t=-4 and ends at t=-1 - again still 3ns. This would be tSU=4, tH=-1.

All of these have a 3ns required data valid window, which means that tSU + tH = 3ns. Remember that for the set_output_delay, the -max is the required setup time and the -min is the negative of the required hold time. So for our 3 cases we would have

a) max=1, min = -2

b) max= -1, min = -4

c) max =4, min = 1

In all three of these cases, the min is smaller than the max, which is required (and makes sense - how can a min be greater than a max)

Now yours; your max = -1 (tSU=-1) and your min = -1 (tH = 1). This means that the required window starts 1ns after the edge of the clock and ends 1ns after the edge of the clock. This means that the device doesn't actually need a valid data window (well, it needs an instantaneous one). No real device can have this kind of characteristic.

Avrum

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inst_npn

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07-17-2017 07:22 PM

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Registered:
06-30-2017

Thanks Avrum. This explains a lot.

So anytime a hold time requirement, x, is given for an external device in a datasheet, the set_output_delay -min value, I should write the constraints as follows, no matter x is given negative or positive value?

set_output_delay -clock CLK -min -x [get_ports out]

Is it same for the set_input_delay -max/-min constraints?

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avrumw

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07-17-2017 08:48 PM

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Registered:
01-23-2009

I should write the constraints as follows, no matter x is given negative or positive value?

The set_output_delay -min is the negative of the hold requirement. If the device needs +2ns of hold, then the set_output_delay -min is -2. If the device needs -2ns of hold time, then the set_output_delay -min is 2.

Is it same for the set_input_delay -max/-min constraints?

No. The set_input_delay -min and -max are the minumum and maximum propagation delay from the clock to the data valid.

The reason that the set_output_delay -min requires the negative value is the direction of time when describing these values. The set_input_delay values are forward propagation delays - moving forward in time; a +2 means 2ns later. For the min and max of the set_input_delay, this is the correct direction.

For the set_output_delays, they are "backward" propagations; they are subtracted off the arrival time of the clock. For them, a positive value is a negative time propagation. Thus if the set_output_delay -max is 2ns, then the data must be ready 2ns **earlier** than the clock. This direction is consistent with the setup measure, since it, too, is measured moving backward in time (from the clock edge toward earlier times). For the hold time, though, it is moving the other way - a positive hold time is moving toward later times - but since the set_output_delay is moving toward earlier times, the hold time needs to be negated.

Avrum

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inst_npn

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07-17-2017 09:25 PM

9,224 Views

Registered:
06-30-2017

Thanks Avrum.

This explanation is exactly what I was looking for.