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Participant kwiatlab
Participant
12,240 Views
Registered: ‎01-19-2012

Simple Offset IN question

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Hello,

 

I am working on building a system synchronous interface and am using Figure 2-2 on Page 15 of

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug612.pdf

for reference.

 

My data becomes valid 1.1ns after the transmit edge and stays valid for 1.4ns. Attached is a simple drawing of the situation.

 

timing.jpg

 

I have the time constraints below, and I just want to make sure they're right -- as I'm kind of new to this. All of the example has OFFSET IN BEFORE, so just making sure this is right.

 

 

NET "CLKINp" TNM_NET = "CLKINp";
TIMESPEC "TS_CLKINp" = PERIOD "CLKINp" 1.6 ns HIGH 50%;
OFFSET = IN 0.5 ns VALID 0.9 ns AFTER "CLKINp";

 

 

 

Thank you for all your time.

 

Michael

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Instructor
Instructor
19,384 Views
Registered: ‎08-14-2007

Re: Simple Offset IN question

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@kwiatlab wrote:

Hmm, okay well thank you both for the replies.

 

Well I'm still slightly confused because although I think the clock before and clock after cases should be equivalent, the clock after case meets my timing while the clock before case does not. It turns out not to be that important for this particular design, but I am still curious as to why timing would fail if the constraints are equivalent.

 

 


The way you wrote the constraint is not equivalent to the way I wrote it.  For OFFSET IN AFTER, you need to use the clock to out delay rather than the input setup time.  The tools will then calculate the setup time using your period spec.  So in the case of your diagram it should look like:

 

OFFSET = IN 1.1 ns VALID 1.4 ns AFTER "CLKINp";

 

Note two things:

 

1) For offset in AFTER you need the time from the privious rising clock edge until the signal becomes valid, in your case 1.1 ns.  The tools will subtract this from the 1.6 ns period to infer an 0.5 ns setup time requirement.  The way you wrote the offset in AFTER constraint the tools thought you had 1.1 ns of setup time, which probably helped them to meet timing.

 

2) For either offset in BEFORE or offset in AFTER, the VALID time refers to the total data valid window, in your case 1.4 ns, and is not referenced to the clock edge.

 

I agree that the syntax for this is clunky when you read it, especially the fact that the VALID timing comes before the BEFORE or AFTER keyword, making it look like the VALID time is referenced to the clock.  As I said, the VALID time is referenced to the start of validity, in your case 1.1 ns after a clock edge and 0.5 ns before the next.  For someone used to working with setup and hold times directly this requires back-calculation to get the proper valid window (VALID = setup + hold, where either can be negative numbers).

 

-- Gabor
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6 Replies
Xilinx Employee
Xilinx Employee
12,223 Views
Registered: ‎08-02-2007

Re: Simple Offset IN question

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Hi,

 

Refer to the WP http://www.xilinx.com/support/documentation/white_papers/wp237.pdf page16 talks about offset in after.

 

This looks fine to me. My two cents :)

 

--Hem

 

 

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Instructor
Instructor
12,213 Views
Registered: ‎08-14-2007

Re: Simple Offset IN question

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To match the timing in your diagram, the correct OFFSET IN should be:

 

OFFSET = IN 0.5 ns VALID 1.4 ns BEFORE "CLKINp";

 

I've never used OFFSET IN AFTER because it generally makes no sense for setup and hold time.

 

The way I wrote it it means:

 

Data becomes valid 0.5 ns before the edge of CLKINp and remains valid for 1.4 ns total (not from the clock edge).

-- Gabor
Participant kwiatlab
Participant
12,188 Views
Registered: ‎01-19-2012

Re: Simple Offset IN question

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Hmm, okay well thank you both for the replies.

 

Well I'm still slightly confused because although I think the clock before and clock after cases should be equivalent, the clock after case meets my timing while the clock before case does not. It turns out not to be that important for this particular design, but I am still curious as to why timing would fail if the constraints are equivalent.

 

 

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Xilinx Employee
Xilinx Employee
12,184 Views
Registered: ‎07-16-2008

Re: Simple Offset IN question

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OFFSET IN BEFORE and OFFSET IN AFTER don't have equivalent requirements.

OFFSET IN BEFORE takes the "capture clock edge" as the reference, while OFFSET IN AFTER takes the "launch clock edge (transmit clock in your picture)" as the reference.

 

As Hem mentioned, please refer to the following white paper for more information.

http://www.xilinx.com/support/documentation/white_papers/wp237.pdf

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Instructor
Instructor
19,385 Views
Registered: ‎08-14-2007

Re: Simple Offset IN question

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@kwiatlab wrote:

Hmm, okay well thank you both for the replies.

 

Well I'm still slightly confused because although I think the clock before and clock after cases should be equivalent, the clock after case meets my timing while the clock before case does not. It turns out not to be that important for this particular design, but I am still curious as to why timing would fail if the constraints are equivalent.

 

 


The way you wrote the constraint is not equivalent to the way I wrote it.  For OFFSET IN AFTER, you need to use the clock to out delay rather than the input setup time.  The tools will then calculate the setup time using your period spec.  So in the case of your diagram it should look like:

 

OFFSET = IN 1.1 ns VALID 1.4 ns AFTER "CLKINp";

 

Note two things:

 

1) For offset in AFTER you need the time from the privious rising clock edge until the signal becomes valid, in your case 1.1 ns.  The tools will subtract this from the 1.6 ns period to infer an 0.5 ns setup time requirement.  The way you wrote the offset in AFTER constraint the tools thought you had 1.1 ns of setup time, which probably helped them to meet timing.

 

2) For either offset in BEFORE or offset in AFTER, the VALID time refers to the total data valid window, in your case 1.4 ns, and is not referenced to the clock edge.

 

I agree that the syntax for this is clunky when you read it, especially the fact that the VALID timing comes before the BEFORE or AFTER keyword, making it look like the VALID time is referenced to the clock.  As I said, the VALID time is referenced to the start of validity, in your case 1.1 ns after a clock edge and 0.5 ns before the next.  For someone used to working with setup and hold times directly this requires back-calculation to get the proper valid window (VALID = setup + hold, where either can be negative numbers).

 

-- Gabor
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Participant kwiatlab
Participant
12,146 Views
Registered: ‎01-19-2012

Re: Simple Offset IN question

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Ah okay the differing clock edges explains it very well. Thank you for all the replies, I was just getting confused in the syntax, which is kind of awkward. Makes much more sense now.

 

 

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