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diverger
Adventurer
Adventurer
353 Views
Registered: ‎06-22-2018

Source or System Synchronous when the data is clocked in by a clock generated by FPGA

Hi,

I have an ADC clocked by a clock generated by the Zynq,  then which synchronous constraint I should use? 

 

Thanks. 

6 Replies
viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

What is the period and phase relationship between the ADC source clock and the capture clock in FPGA?

-vivian

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diverger
Adventurer
Adventurer
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Registered: ‎06-22-2018

@viviany 

The ADC data will be clocked out by the rising or falling edge (it can be configured). Assuming using rising edge to clock out the data, the data will be valid 5ns after the rising edge.

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

As an asside, 

is the clock form the FPGA constant, and is it used by the ADC to sample the analog input ?

If so , you need to check that the clock is clean enough to get the required number of bits from the ADC, 

 

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avrumw
Guide
Guide
256 Views
Registered: ‎01-23-2009

I have an ADC clocked by a clock generated by the Zynq,  then which synchronous constraint I should use? 

Both... Neither...

There is no official name for this kind of an interface, I refer to it as "worse than system synchronous". Take a look at this post on worse than system synchronous interfaces and their constraints.

Avrum

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diverger
Adventurer
Adventurer
185 Views
Registered: ‎06-22-2018

Yes, the clock is used by ADC to sample the input. And the clock from FPGA may be changed at runtime, it will be generated using Clocking Wizard.

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drjohnsmith
Teacher
Teacher
161 Views
Registered: ‎07-09-2009

https://training.ti.com/understanding-clock-jitter-impact-adc-snr

 

What is your max sampling frequency, your max analog bandwidth and the number of bits in the adc ?

 

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