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Adventurer
Adventurer
304 Views
Registered: ‎06-30-2013

Source synchronous DDR interface - fundamental issue with setup and hold

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I have implemented a centered source synchronous LVDS DDR interface in a Zynq with Kintex fabric.    The interface only uses IDELAYE2 elements for the 8 data lanes and no delay for the clock.  The clock is fed to both the IDDRs and the fabric through a BUFR.  No BUFIOs are used because static timing was better with the BUFR.  The ADC interface operates at 200MHz and I was able to just barely pass static timing by tuning the individual IDELAYE2 elements for each lane

From previous forum discussion,  it has been made clear from avrumw and others that dynamic timing with a training pattern and the use of ISERDES would be the better approach.

In my current implementation I have several prototypes which are operating even with setup and hold slacks that are positive but are less than 30ps - well less than the 78ps tap resolution of the IDELAYE2 elements.

However, what has me very confused, most likely due to some fundamental lack of understanding is that if I send out an all zero value on my 8-lane DDR interface,  I see in one unit, that has one bit is not always received as a zero.  Seven of the eight lanes are correctly received.

I have verified that the differential data lines very near to the two FPGA input pins is indeed a constant zero level - it is static.  From my perspective, this should mean that there is no data changing at either the rising or falling edge of the clock at the D input to the IDDR element for the bit pair.

My understanding is that even if I had a setup or hold violation at the IDDR, the fact that the data bit input to the IDDR is static should mean that the output should not change.  I understand if the data was changing on each edge that metastability would give erroneous results but the data at the FPGA input pins is not changing so what mechanism is causing the IDDR output to be other than zero?

Thanks in advance for any explanation that could explain what is going on here.

Craig

 

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Historian
Historian
264 Views
Registered: ‎01-23-2009

Re: Source synchronous DDR interface - fundamental issue with setup and hold

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My understanding is that even if I had a setup or hold violation at the IDDR, the fact that the data bit input to the IDDR is static should mean that the output should not change. 

By definition, a setup or hold violation is when the data makes a transition within the setup/hold window of the sampling flip-flop. If there are no transitions, then by definition there are no setup/hold violations. Sampling a static 0 (on any clock) with an IDDR should always result in the outputs of the IDDR being 0. This is not a timing problem.

Therefore this must be something else. I can't tell you what - maybe the separation between the P and the N is not large enough for the input to be considered a valid 0 (but you say you measured it) - maybe the termination is not correct. Are you sure the input is not AC coupled (an AC coupled input cannot be allowed to take a static value for an extended period of time)? Are you sure the PIN_LOCATIONs are correct, and you aren't accidentally looking at another signal? But it is not a timing problem.

From previous forum discussion,  it has been made clear from avrumw and others that dynamic timing with a training pattern and the use of ISERDES would be the better approach.

I am pretty sure I never said that! I hate dynamic calibration systems - take a look at this post on dynamic capture... In my opinion it is only to be used when there is no other way to accomplish what you want. If you have the interface meeting timing from the tools - even with 30ps of slack (assuming your constraints are 100% correct, including any derating for signal integrity and clock jitter), then I would go with that over dynamic calibration.

Avrum

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2 Replies
Historian
Historian
265 Views
Registered: ‎01-23-2009

Re: Source synchronous DDR interface - fundamental issue with setup and hold

Jump to solution

My understanding is that even if I had a setup or hold violation at the IDDR, the fact that the data bit input to the IDDR is static should mean that the output should not change. 

By definition, a setup or hold violation is when the data makes a transition within the setup/hold window of the sampling flip-flop. If there are no transitions, then by definition there are no setup/hold violations. Sampling a static 0 (on any clock) with an IDDR should always result in the outputs of the IDDR being 0. This is not a timing problem.

Therefore this must be something else. I can't tell you what - maybe the separation between the P and the N is not large enough for the input to be considered a valid 0 (but you say you measured it) - maybe the termination is not correct. Are you sure the input is not AC coupled (an AC coupled input cannot be allowed to take a static value for an extended period of time)? Are you sure the PIN_LOCATIONs are correct, and you aren't accidentally looking at another signal? But it is not a timing problem.

From previous forum discussion,  it has been made clear from avrumw and others that dynamic timing with a training pattern and the use of ISERDES would be the better approach.

I am pretty sure I never said that! I hate dynamic calibration systems - take a look at this post on dynamic capture... In my opinion it is only to be used when there is no other way to accomplish what you want. If you have the interface meeting timing from the tools - even with 30ps of slack (assuming your constraints are 100% correct, including any derating for signal integrity and clock jitter), then I would go with that over dynamic calibration.

Avrum

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Adventurer
Adventurer
224 Views
Registered: ‎06-30-2013

Re: Source synchronous DDR interface - fundamental issue with setup and hold

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Hi avrumw:

I am very embarrassed to admit that I made a probing error and reached an erroneous conclusion.  It turns out that the OIDDR that was changing was driven by an external driver that was indeed damaged and was not always driving legitimate LVDS levels.

But thank you for the response - at least I thought I understood the basics and your reply confirmed that.

It turns out that in my design, I had per bit IDELAYE tap control and I found that I could vary the delay about +/- 8 taps for the other working DDR bits and still capture valid data.  I think I have enough headroom to live with my static timing closure.

Thanks again,

Craig

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