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Voyager
Voyager
546 Views
Registered: ‎05-30-2018

Specified Timing constraint wasn't taken into account

Hello,

I created a constraint for derivative clock, then saved it in the default constraint file (at least Vivado indicated that new constraint saved) and finally proceeded with synthesis/implementation.

After implementation to my big surprise I discovered that my new constraint wasn't taken into account by implementation ... moreover I didn't find it in the constraint file.

Any comments ?

Thanks.

 

P.S. Timing constraint "view" after specifying new "Create Generated Clock" constraint in the constraints_1.sdc.

generated_clock_constraint_specified_that_disappears.png

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17 Replies
Moderator
Moderator
539 Views
Registered: ‎11-04-2010

Re: Specified Timing constraint wasn't taken into account

Hi, @pavel_47 ,

1. Please confirm the create_generated_clock constraint is written correctly.

    <1> Open the implemented design

    <2> Run your create_generated_clock constraint in TCL Console

    <3> Run report_clocks to check whether the

2. Confirm in the project your create_generated_clock constraint is executed after the create_clock constaint for the input clock of MMCM/PLL. 

PS:  If you only need to modify the clock name of the derived clock, you don't need to set -multiple_by option.

 

 

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Voyager
Voyager
520 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

Hi Hongh,

This is how I proceeded:

  1. Synthesized/implemented design
  2. Found timing violations on several inetrnal datapaths (negative slack)
  3. Found huge quantity (4499) "no clock" violations (please see screenshot below)
  4. Created generated_clock constraint on several pins from the "no clock" list (hoping that applying such constraints could resolve timing violation issues)
  5. Saved new generated_clock constraint in the project constraint files
  6. Rerun synthesis/implementation
  7. Opened implemented design
  8. Found that nothing changed comparing with previous synthesis/implementation run
  9. Found that previously creared & saved generated_clock constraint disappeared

Where I've been mistaken in my approach.

Actually I have no access to my design - I will try your suggestion tomorrow morning.

Thanks.

clock_issues_while_synthesizing_isg001.png

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Xilinx Employee
Xilinx Employee
503 Views
Registered: ‎05-14-2008

Re: Specified Timing constraint wasn't taken into account

Several things to check:

"4.Created generated_clock constraint on several pins from the "no clock" list (hoping that applying such constraints could resolve timing violation issues)

5.Saved new generated_clock constraint in the project constraint files"

How did you add the create_generated_clock constraint? In the tcl console? In the Timing constraints Editor? Was there any warning message returned indicating any problem with this constraint right after you added it?

How did you save the new constraint? Press any button or something? Have you opened the XDC file in a text editor to check if the create_generated_clock constraint was indeed in it?

Why don't you manually add the constraint to "constraints_1.xdc" directly?

And have you figured out why you have so many no_clock pins? Generated clock is usually created on a common node (common clock driver that then fanouts to many clock pins) rather than on a C pin of the loads. For example, the Q pin of a register that is generating a derived clock, the O pin of a LUT that works as a clock mux. If you can show what your clock network is like in your design, we can provide suggestions on clock constraint.

-vivian

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Voyager
Voyager
491 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

Here is a diagram that visualizes the problem (for 2nd line - ...reg[0]/C)::

no_clock_violation_schematics.png

I add new constraint using Timing constraints Editor.

Here it is:

create_generated_clock -name clock_generated_1 -source [get_ports "*dfe_clk*"] -multiply_by 1 [get_pins dfe_clk_IBUF_BUFG_inst/O]

Tiday I could save it in constraint file. Yesterday I generated it in different way and after presumed saving I checked constraint file and saw that new constraint was absent in constraint file. At that moment I was thinking that it was some kind of vivado bug ... i.e. constraint file wasn't properly updated. Probably there was some syntax error ... and my constraint was merely rejected.

The new constraint I generated today seems to be also erroneous.

Here is the fragment of output of  report_clocks:

Clock Period(ns) Waveform(ns) Attributes Sources
design_1_i/clk_wiz_0/inst/clk_in141.667 {0.000 20.833} P {design_1_i/clk_wiz_0/inst/clk_in1}
clkfbout_design_1_clk_wiz_0_0 41.667 {0.000 20.833} P,G,A {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT}
clk_out1_design_1_clk_wiz_0_0 12.500 {0.000 6.250} P,G,A {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0}
clock_generated_1 0.000 {} P,G {dfe_clk_IBUF_BUFG_inst/O}

In the last line - my new constraint. Period - 0, waveform - empty.

Thanks.

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Xilinx Employee
Xilinx Employee
482 Views
Registered: ‎05-14-2008

Re: Specified Timing constraint wasn't taken into account

Looks like the create_clock constraint in your PLL IP fails to be applied to the dfe_clk port.

Not sure what's going wrong here. May be related to some incorrect setting in your PLL IP.

However, manally adding the create_clock constraint for dfe_clk in your user XDC should resolve the issue.

create_clock -name dfe_clk -period 41.667 [get_ports dfe_clk]

 

And you do not need the create_generated_clock constraint. The clock should be propagated automatically through IBUF and BUFG. As long as the clock is defined on dfe_clk port, you'll get rid of those no_clock violations.

-vivian

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Voyager
Voyager
479 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

There is something perplexing with the tming constraint management staff.

Sometimes saving new constrint into constraint file works, sometimes - no.

I've modified the new constraint and saved it (at least I proceeded with "save action").

Then, after switching to constraint file, I've noticed old version of clock_generated_1 constraint.

Anyway I added it manually:

#create_generated_clock -name clock_generated_1 -source [get_ports *dfe_clk*] -multiply_by 1 [get_pins dfe_clk_IBUF_BUFG_inst/O]
create_generated_clock -name clock_generated_1 -source [get_pins design_1_i/clk_wiz_0/inst/clk_out1] -multiply_by 1 [get_pins dfe_clk_IBUF_BUFG_inst/O]

Then I checked new version of clock_generated_1 constraint with report_clocks, and that time it seems to be Ok:

Clock Period(ns) Waveform(ns) Attributes Sources
design_1_i/clk_wiz_0/inst/clk_in1 41.667 {0.000 20.833} P {design_1_i/clk_wiz_0/inst/clk_in1}
clkfbout_design_1_clk_wiz_0_0 41.667 {0.000 20.833} P,G,A {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT}
clk_out1_design_1_clk_wiz_0_0 12.500 {0.000 6.250} P,G,A {design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0}
clock_generated_1 12.500 {0.000 6.250} P,G {dfe_clk_IBUF_BUFG_inst/O}

and rerurn synthesis/implementation.

Unfortunately applying of the clock_generated_1 constraint didn't help: the problem of huge number of "no clock" persists.

Any suggestions ?

Thanks.

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Xilinx Employee
Xilinx Employee
470 Views
Registered: ‎05-14-2008

Re: Specified Timing constraint wasn't taken into account

“create_generated_clock -name clock_generated_1 -source [get_pins design_1_i/clk_wiz_0/inst/clk_out1] -multiply_by 1 [get_pins dfe_clk_IBUF_BUFG_inst/O]”

This constaint is not correct. The clock on dfe_clk_IBUF_BUFG_inst/O is not derived from "design_1_i/clk_wiz_0/inst/clk_out1", correct?

You don't show the PLL in your schematic, but the  dfe_clk_IBUF_BUFG_inst is connected to the clock port, not the output of the PLL.

Your problem is, you don't define the clock on dfe_clk port but use the create_clock constraint inside the PLL IP.

Does the PLL input clock come from dfe_clk port? Can you show schematic how this PLL is connected in your design?

 

Anyway, user should give create_clock constraint explicitely in user XDC (constraints_1.xdc) for input clock port. 

According to your schematic above, adding this clock in constraints_1.xdc will resolve the no_clock pins that are drivin by the clock net from dfe_clk_IBUF_BUFG_inst.

Again, clock on a BUFG/O pin do not need a create_generated_clock constraint. Clocks are propagated automatically through IBUF and BUFG as long as there is clock defined on the input clock port.

If you still have other no_clock pins, those are related to other clock source.

-vivian

 

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Voyager
Voyager
463 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

Thanks Vivian,

Indded, I was mistaken with this constraint.

I followed your suggestion and applied constraint on the external clock port dfe_clk (and also to another one) ... added manually to .xdc.

create_clock -name dfe_clk -period 41.667 [get_ports dfe_clk]
create_clock -period 20.000 -name clk_spi -waveform {0.000 10.000} [get_ports i_spis_sck]

Now it's much better: only 168 "no clock" constraints (schematic corresponds to the 1st line):

no_clock_violation_schematics1.png

That time applying of the "generated clock" is probably necessary ?

thanks 

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Xilinx Employee
Xilinx Employee
453 Views
Registered: ‎05-14-2008

Re: Specified Timing constraint wasn't taken into account

Yes, this clock is generted by a register. You need to add create_generated_clock for this one.

create_generated_clock -name xxx  -source [get_pins <the register cell name>/C] -multiply_by  x  (or -divide_by x or both) [get_pins <the register cell name>/Q]

in which the register cell name is referring to the register that is generating the clock.

-vivian

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Voyager
Voyager
451 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

I've added also "clock desynchronized" constraint

set_clock_groups -name group_1 -asynchronous -group [get_clocks {clk_spi dfe_clk}]

but it seems that it didn't work:

clock_to_clock_violations1.png

One more question: is there some way to "export" a constraint, created in Timing Constraint Editor directly to .xdc, ... or one must proceed with copy/past ?

Thanks.

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Voyager
Voyager
445 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account


@viviany wrote:

Yes, this clock is generted by a register. You need to add create_generated_clock for this one.

create_generated_clock -name xxx  -source [get_pins <the register cell name>/C] -multiply_by  x  (or -divide_by x or both) [get_pins <the register cell name>/Q]

in which the register cell name is referring to the register that is generating the clock.

-vivian


Using schematic, the cell name is plle2_adv_inst , C corresponds to CLKIN1 and Q to CLKOUT0, Correct ?

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Voyager
Voyager
426 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

Well ... here is generated_clock constraint, that creates clock at the output of PLL (24MHz  --> 80 MHz ):

create_generated_clock -name clk_80MHz -source [get_ports dfe_clk] -divide_by 3 -multiply_by 10 [get_pins design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0]

Most likely it's not correct because:

  • it doesn't resolve "no clock" violations
  • it causes negative setup violation with respect to clock it originates from

Here is clock group constraint, that separates 2 clock domains:

set_clock_groups -asynchronous -group {clk_spi} -group {dfe_clk clkfbout_design_1_clk_wiz_0_0 design_1_i/clk_wiz_0/inst/clk_in1 clk_80MHz}

The derived clock clk_80MHz is put in the same domain as dfe_clk, but timing analysis outputs this:

clk_80MHz_to_dfe_clk_negative_setup.png

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Voyager
Voyager
419 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

The constraint that creates clk_80MHz is completely wrong.

The issue is caused by the fact that clock for the register that folow is generated by state machine, i.e.:

	line_cnt_clk <= '1' when curr_state = INTERRUPT_GEN else '0';
	line_cnt_rst <= frame_start;
	LINES_COUNTER: process(line_cnt_clk, line_cnt_rst)
	begin
		if line_cnt_rst = '1' then
			line_cnt <= (others => '0');
		elsif rising_edge(line_cnt_clk) then
			line_cnt <= line_cnt + 1;
		end if;
	end process LINES_COUNTER;

Does exist some workaround or it will be better to change the code ?

Thanks.

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Voyager
Voyager
408 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account

Well, this modification resolved issue:

	line_cnt_rst <= frame_start;
	LINES_COUNTER: process(clk, line_cnt_rst)
	begin
		if line_cnt_rst = '1' then
			line_cnt <= (others => '0');
		elsif rising_edge(clk) then
			if curr_state = INTERRUPT_GEN then
				line_cnt <= line_cnt + 1;
			end if;
		end if;
	end process LINES_COUNTER;
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Xilinx Employee
Xilinx Employee
390 Views
Registered: ‎05-14-2008

Re: Specified Timing constraint wasn't taken into account


@pavel_47 wrote:

@viviany wrote:

Yes, this clock is generted by a register. You need to add create_generated_clock for this one.

create_generated_clock -name xxx  -source [get_pins <the register cell name>/C] -multiply_by  x  (or -divide_by x or both) [get_pins <the register cell name>/Q]

in which the register cell name is referring to the register that is generating the clock.

-vivian


Using schematic, the cell name is plle2_adv_inst , C corresponds to CLKIN1 and Q to CLKOUT0, Correct ?


Please note that it's "the register cell name". The register is "FSM_..._state_reg[2]", because the clock net driving those no_clock pins is from the Q pin of this register.

PLL is not a register. Besides, the PLL output clock constraint is automatically added by the tool and its frequency is automatically identified by the tool.

However, a clock cannot be automatically propagated through a register, because the clock frequency is UNKNOWN. So user needs to add create_generated_clock explicitly in this case.

-vivian

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generated_clock_reg.png
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Xilinx Employee
Xilinx Employee
386 Views
Registered: ‎05-14-2008

Re: Specified Timing constraint wasn't taken into account


@pavel_47 wrote:

Well ... here is generated_clock constraint, that creates clock at the output of PLL (24MHz  --> 80 MHz ):

create_generated_clock -name clk_80MHz -source [get_ports dfe_clk] -divide_by 3 -multiply_by 10 [get_pins design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0]

Most likely it's not correct because:

  • it doesn't resolve "no clock" violations
  • it causes negative setup violation with respect to clock it originates from

Here is clock group constraint, that separates 2 clock domains:

set_clock_groups -asynchronous -group {clk_spi} -group {dfe_clk clkfbout_design_1_clk_wiz_0_0 design_1_i/clk_wiz_0/inst/clk_in1 clk_80MHz}

The derived clock clk_80MHz is put in the same domain as dfe_clk, but timing analysis outputs this:

 


What are you expecting with the set_clock_groups constraint? 

If you'd like to make two clocks asynchronous, they should be put into different -group options.

E.g.

set_clock_groups -asynchronous -group {dfe_clk} -group {clk_80MHz}

If two clocks are in the same group, they are synchronous and Vivado will do cross-domain timing analysis between the two clocks, like you see in your timing report.

-vivian

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Voyager
Voyager
376 Views
Registered: ‎05-30-2018

Re: Specified Timing constraint wasn't taken into account


@viviany wrote:

@pavel_47 wrote:

Well ... here is generated_clock constraint, that creates clock at the output of PLL (24MHz  --> 80 MHz ):

create_generated_clock -name clk_80MHz -source [get_ports dfe_clk] -divide_by 3 -multiply_by 10 [get_pins design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0]

Most likely it's not correct because:

  • it doesn't resolve "no clock" violations
  • it causes negative setup violation with respect to clock it originates from

Here is clock group constraint, that separates 2 clock domains:

set_clock_groups -asynchronous -group {clk_spi} -group {dfe_clk clkfbout_design_1_clk_wiz_0_0 design_1_i/clk_wiz_0/inst/clk_in1 clk_80MHz}

The derived clock clk_80MHz is put in the same domain as dfe_clk, but timing analysis outputs this:

 


What are you expecting with the set_clock_groups constraint? 

If you'd like to make two clocks asynchronous, they should be put into different -group options.

E.g.

set_clock_groups -asynchronous -group {dfe_clk} -group {clk_80MHz}

If two clocks are in the same group, they are synchronous and Vivado will do cross-domain timing analysis between the two clocks, like you see in your timing report.

-vivian


Yes, I corrected it in my later posts.

Thanks.

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