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caslaba
Newbie
Newbie
6,285 Views
Registered: ‎03-05-2013

Speed of a circuit without I/O

I am designing a interior circuit that has no IO connections. ( I have unchecked" Add IO Buffers" from synthesis options and "trim unconnected signals" from map properties )

 

The circuit flow is such that; ( only one clock exists)

 

INPUT => flip flop => Block RAM =>  Combinational Logic => Flip Flop => OUTPUT .

 

I must take the max clocking speed with regarding the circuit as an interior FPGA design with no IO delay.

 

Thanks.

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3 Replies
bassman59
Historian
Historian
6,279 Views
Registered: ‎02-25-2008


@caslaba wrote:

I am designing a interior circuit that has no IO connections. ( I have unchecked" Add IO Buffers" from synthesis options and "trim unconnected signals" from map properties )

 

The circuit flow is such that; ( only one clock exists)

 

INPUT => flip flop => Block RAM =>  Combinational Logic => Flip Flop => OUTPUT .

 

I must take the max clocking speed with regarding the circuit as an interior FPGA design with no IO delay.

 

Thanks.


you're going backwards.

You set a timing constraint based on the target period you're trying to achieve, and the tools work to meet that constraint.

Without a constraint, the tools will do the easiest/laziest thing, which may or may not be the fastest possible path.

----------------------------Yes, I do this for a living.
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hasaney
Adventurer
Adventurer
6,270 Views
Registered: ‎03-06-2011

Thanks,

 

I don't understand the going backwards WHY?

 

If i set a constraint, CLK speed is shown. However without a constraint on CLK, there is no timing report about max frequncy of CLK. In general which I saw until now, P&R report gives to CLK speed without introducing a CLK constraint.

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bassman59
Historian
Historian
6,257 Views
Registered: ‎02-25-2008


@hasaney wrote:

Thanks,

 

I don't understand the going backwards WHY?

 

If i set a constraint, CLK speed is shown. However without a constraint on CLK, there is no timing report about max frequncy of CLK. In general which I saw until now, P&R report gives to CLK speed without introducing a CLK constraint.


AGAIN: Without setting a constraint, the tools will do whatever's easiest. They will report the clock frequency which results.

 

If you are interested in actual performance metrics you need to set a timing constraint.

----------------------------Yes, I do this for a living.