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Adventurer
Adventurer
341 Views
Registered: ‎10-31-2017

Still struggling with a system synchronous output delay constraint

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This has already been discussed in another thread amongst other ouput related timings. I am strill fighting with the constraints for these outpus.

Device is Zynq7000 and tool is Vivado 2.18.3.

 

The problematic PL outputs are connected to a high speed DAC. The data outputs must be ready 5.1ns before the rising edge of the input clock, already considering the track lenghs (very short), the level translator maximum delay (3.3ns) and D/A min setup time (1.6ns). The clock that feeds the D/A is in phase with the clock that feeds the FPGA, other than a small skew due to different track lenghs.

So I set the following constraints for those outputs:

create_clock -period 12.500 -name virt_clk
set_output_delay -clock virt_clk -max 5.150 [get_ports {o_DacData[*]}]

I am getting the following error:

-------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Mon Mar 25 16:16:43 2019
| Host         : TIMPEL-PD-0273 running 64-bit major release  (build 9200)
| Command      : report_timing -from [get_pins {SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/DataOut_reg[9]/C}] -to [get_ports {o_DacData[9]}] -setup
| Design       : SAR_ZYNQ_wrapper
| Device       : 7z020-clg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
-------------------------------------------------------------------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) :        -11.953ns  (required time - arrival time)
  Source:                 SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/DataOut_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0  {rise@-1.953ns fall@4.297ns period=12.500ns})
  Destination:            o_DacData[9]
                            (output port clocked by virt_clk  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             virt_clk
  Path Type:              Max at Slow Process Corner
  Requirement:            1.953ns  (virt_clk rise@12.500ns - clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0 rise@10.547ns)
  Data Path Delay:        3.421ns  (logic 3.420ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           5.150ns
  Clock Path Skew:        -5.110ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 12.500 - 12.500 ) 
    Source Clock Delay      (SCD):    5.110ns = ( 15.657 - 10.547 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.225ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.172ns
    Phase Error              (PE):    0.136ns
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0 rise edge)
                                                     10.547    10.547 r  
    M19                                               0.000    10.547 r  CLK_SYS_P (IN)
                         net (fo=0)                   0.000    10.547    SAR_ZYNQ_i/util_ds_buf_0/U0/IBUF_DS_P[0]
    M19                  IBUFDS (Prop_ibufds_I_O)     0.905    11.452 r  SAR_ZYNQ_i/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O
                         net (fo=1, routed)           2.205    13.657    SAR_ZYNQ_i/clk_wiz_0/inst/clk_in1
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.102    13.759 r  SAR_ZYNQ_i/clk_wiz_0/inst/clkin1_bufg/O
                         net (fo=1, routed)           1.806    15.565    SAR_ZYNQ_i/clk_wiz_0/inst/clk_in1_SAR_ZYNQ_clk_wiz_0_0
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.793    11.772 r  SAR_ZYNQ_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.889    13.661    SAR_ZYNQ_i/clk_wiz_0/inst/clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.101    13.762 r  SAR_ZYNQ_i/clk_wiz_0/inst/clkout1_buf/O
                         net (fo=14, routed)          1.894    15.657    SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/Clk_DAC
    OLOGIC_X1Y33         FDCE                                         r  SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/DataOut_reg[9]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y33         FDCE (Prop_fdce_C_Q)         0.472    16.129 r  SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/DataOut_reg[9]/Q
                         net (fo=1, routed)           0.001    16.130    o_DacData_OBUF[9]
    AB21                 OBUF (Prop_obuf_I_O)         2.948    19.078 r  o_DacData_OBUF[9]_inst/O
                         net (fo=0)                   0.000    19.078    o_DacData[9]
    AB21                                                              r  o_DacData[9] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock virt_clk rise edge)
                                                     12.500    12.500 r  
                         ideal clock network latency
                                                      0.000    12.500    
                         clock pessimism              0.000    12.500    
                         clock uncertainty           -0.225    12.275    
                         output delay                -5.150     7.125    
  -------------------------------------------------------------------
                         required time                          7.125    
                         arrival time                         -19.078    
  -------------------------------------------------------------------
                         slack                                -11.953    

The tool is considering the outputs delays relative to the rising edge at 12.5ns (or its clock clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0 counterpart) for both the constraint and the output delay, whereas I thought it should consider the output delay from the initial rise time to determing the setup from the second. What am I missing?

 

Also, it is not clear to me why the timing starts at 10.547ns.

 

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1 Solution

Accepted Solutions
288 Views
Registered: ‎01-22-2015

Re: Still struggling with a system synchronous output delay constraint

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Hi Elder,

   I stopped using $variables because the wizard wipe them out and replace with numeric values.
   ....but for some reason the line vanished.
Yes, these are maddening problems of the Vivado Constraints Wizard.  The Constraints Wizard concept is a good idea, but the existing Constraints Wizard makes such a mess of your constraints (XDC) file, that I do not recommend using it. 

   However, I recalled you advised me to use set_property PHASESHIFT_MODE LATENCY [get_cells <instance_name>]
You still need this constraint.  It should look like the following:

set_property PHASESHIFT_MODE LATENCY [get_cells {SAR_ZYNQ_i/clk_wiz_0/inst/mmcm_adv_inst}]

Cheers,
Mark

 

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5 Replies
324 Views
Registered: ‎01-22-2015

Re: Still struggling with a system synchronous output delay constraint

Jump to solution

Hi Elder,

     This has already been discussed in another thread amongst other ouput related timings. I am strill fighting with the constraints for these outpus.
Below is the template from the other thread for creating the constraints.  Please try copying it into your XDC file, replacing the numbers with numbers of your own.

#(all delays and times below are in nanoseconds)
#max external clock-path-delay to the FPGA port, CLK_SYS_P
set clkf_max 0.200
#min external clock-path-delay to the FPGA port, CLK_SYS_P
set clkf_min 0.150
#max external clock-path-delay to the D/A register
set clkd_max 0.250
#min external clock-path-delay to the D/A register
set clkd_min 0.200
#max external data-path-delay to the D/A register
set datd_max 0.150
#min external data-path-delay to the D/A register
set datd_min 0.130
#setup time of the D/A register
set tsu 2.400
#hold time of the D/A register
set thd 0.100
#create the virtual input clock (must have same period as external low jitter clock generator)
create_clock -name virt_clk -period 12.5
set_output_delay -clock virt_clk -max [expr $clkf_max + $datd_max - $clkd_min + $tsu] [get_ports {o_DacData[*]}]
set_output_delay -clock virt_clk -min [expr $clkf_min + $datd_min - $clkd_max - $thd] [get_ports {o_DacData[*]}]

Cheers,
Mark

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Adventurer
Adventurer
309 Views
Registered: ‎10-31-2017

Re: Still struggling with a system synchronous output delay constraint

Jump to solution

Hello, Mark,

These commands are  basically what I am using (but with -add_delay to the -min command), except for the setup time value. I stopped using $variables because the wizard wipe them out and replace with numeric values.

However, I recalled you advised me to use set_property PHASESHIFT_MODE LATENCY [get_cells <instance_name>] but for some reason the line vanished (not sure if I deleted it by mistake or something else).

After adding it to the constraints file, the error has gone. I think that is what you meant by "wonky results" should this property not have been set.

------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Mon Mar 25 19:22:50 2019
| Host         : TIMPEL-PD-0273 running 64-bit major release  (build 9200)
| Command      : report_timing -to [get_ports o_DacData*] -setup
| Design       : SAR_ZYNQ_wrapper
| Device       : 7z020-clg484
| Speed File   : -1  PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             0.547ns  (required time - arrival time)
  Source:                 SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/DataOut_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            o_DacData[9]
                            (output port clocked by virt_clk  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             virt_clk
  Path Type:              Max at Slow Process Corner
  Requirement:            12.500ns  (virt_clk rise@12.500ns - clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0 rise@0.000ns)
  Data Path Delay:        3.421ns  (logic 3.420ns (99.971%)  route 0.001ns (0.029%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           5.150ns
  Phase Shift in Clock Latency:
    Source Clock:         -1.953ns
  Clock Path Skew:        -3.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 12.500 - 12.500 ) 
    Source Clock Delay      (SCD):    3.157ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.225ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.172ns
    Phase Error              (PE):    0.136ns
  Clock Domain Crossing:  Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0 rise edge)
                                                      0.000     0.000 r  
    M19                                               0.000     0.000 r  CLK_SYS_P (IN)
                         net (fo=0)                   0.000     0.000    SAR_ZYNQ_i/util_ds_buf_0/U0/IBUF_DS_P[0]
    M19                  IBUFDS (Prop_ibufds_I_O)     0.905     0.905 r  SAR_ZYNQ_i/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O
                         net (fo=1, routed)           2.205     3.110    SAR_ZYNQ_i/clk_wiz_0/inst/clk_in1
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.102     3.212 r  SAR_ZYNQ_i/clk_wiz_0/inst/clkin1_bufg/O
                         net (fo=1, routed)           1.806     5.018    SAR_ZYNQ_i/clk_wiz_0/inst/clk_in1_SAR_ZYNQ_clk_wiz_0_0
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -5.746    -0.728 r  SAR_ZYNQ_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.889     1.161    SAR_ZYNQ_i/clk_wiz_0/inst/clk_80M_DA_SAR_ZYNQ_clk_wiz_0_0
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.101     1.262 r  SAR_ZYNQ_i/clk_wiz_0/inst/clkout1_buf/O
                         net (fo=14, routed)          1.894     3.157    SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/Clk_DAC
    OLOGIC_X1Y33         FDCE                                         r  SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/DataOut_reg[9]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y33         FDCE (Prop_fdce_C_Q)         0.472     3.629 r  SAR_ZYNQ_i/sar_zynq_IP_0/U0/SIGGEN_inst/DataOut_reg[9]/Q
                         net (fo=1, routed)           0.001     3.630    o_DacData_OBUF[9]
    AB21                 OBUF (Prop_obuf_I_O)         2.948     6.578 r  o_DacData_OBUF[9]_inst/O
                         net (fo=0)                   0.000     6.578    o_DacData[9]
    AB21                                                              r  o_DacData[9] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock virt_clk rise edge)
                                                     12.500    12.500 r  
                         ideal clock network latency
                                                      0.000    12.500    
                         clock pessimism              0.000    12.500    
                         clock uncertainty           -0.225    12.275    
                         output delay                -5.150     7.125    
  -------------------------------------------------------------------
                         required time                          7.125    
                         arrival time                          -6.578    
  -------------------------------------------------------------------
                         slack                                  0.547    
0 Kudos
289 Views
Registered: ‎01-22-2015

Re: Still struggling with a system synchronous output delay constraint

Jump to solution

Hi Elder,

   I stopped using $variables because the wizard wipe them out and replace with numeric values.
   ....but for some reason the line vanished.
Yes, these are maddening problems of the Vivado Constraints Wizard.  The Constraints Wizard concept is a good idea, but the existing Constraints Wizard makes such a mess of your constraints (XDC) file, that I do not recommend using it. 

   However, I recalled you advised me to use set_property PHASESHIFT_MODE LATENCY [get_cells <instance_name>]
You still need this constraint.  It should look like the following:

set_property PHASESHIFT_MODE LATENCY [get_cells {SAR_ZYNQ_i/clk_wiz_0/inst/mmcm_adv_inst}]

Cheers,
Mark

 

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Scholar markcurry
Scholar
265 Views
Registered: ‎09-16-2009

Re: Still struggling with a system synchronous output delay constraint

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Can someone point to the "other thread" that's being refered to here?  Markg - that template is great, and deserves kudos. I'd like to understand the entire context - perhaps in the "other thread"?

Thanks,

Mark

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259 Views
Registered: ‎01-22-2015

Re: Still struggling with a system synchronous output delay constraint

Jump to solution
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