1. The GPIO is adding CDC logic and constraints where none are needed, breaking what should be timed paths, and creating confusion.
1. This problem is fixable by creating our own custom GPIO IP for synchronous status bits.
2. But it would be nice if the the GPIO module either automatically only added CDC logic and constraints where necessary, or allowed the user to check a checkbox so that no CDC constraints or logic are added.
3. Or Xilinx could offer a specific purpose I/O (SPIO) IP or synchronous IO (SIO) without CDC logic and without CDC constraints for the benefit or users who prefer not to have unnecessary false paths and interesting clock interaction reports to investigate and explain during design reviews.
I prefer the checkbox option in (2) but (3) is also acceptable.