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Scholar
Scholar
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Registered: ‎06-20-2017

Synchronous IO alternative to GPIO IP?

This should be enough for a xilinx support engineer to file a change request. A scenario to illustrate:

sameclock2.png

 

The EOS (and other signals) goes from the system management through a concat to an AXI GPIO input.

 

In this simple scenario, I am getting a partial false path.

clockInteraction.png

Tracing it by doing slack greater than 100, we get:

FromTo2.png

 


Looking at the path report

 

path.png

 

Which seems to be due to the GPIO IP's scoped to ref constants with wild cards:

set_false_path -to [get_pins -hier *cdc_to*/D] ; # bonus:  two wild cards

 

So, the problem:

1. The GPIO is adding CDC logic and constraints where none are needed, breaking what should be timed paths, and creating confusion.

 

Possible solutions:

1. This problem is fixable by creating our own custom GPIO IP for synchronous status bits.

2. But it would be nice if the the GPIO module either automatically only added CDC logic and constraints where necessary, or allowed the user to check a checkbox so that no CDC constraints or logic are added.

3. Or Xilinx could offer a specific purpose I/O (SPIO) IP or synchronous IO (SIO) without CDC logic and without CDC constraints for the benefit or users who prefer not to have unnecessary false paths and interesting clock interaction reports to investigate and explain during design reviews.

I prefer the checkbox option in (2) but (3) is also acceptable.

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