UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
235 Views
Registered: ‎11-17-2015

TIming analysis of the input delay.

Jump to solution

I am studying the timing analysis on youtube. 

What do the MMCM2_ADV prop_mmcme2_adv_CLKIN1_CLKOUT3 of 6.087 and 5.343 refer to here? 

 

setup.JPG

 

0 Kudos
1 Solution

Accepted Solutions
218 Views
Registered: ‎01-22-2015

Re: TIming analysis of the input delay.

Jump to solution

@lis_user1 

     What do the MMCM2_ADV prop_mmcme2_adv_CLKIN1_CLKOUT3 of 6.087 and 5.343 refer to here?
Since the timing report is showing these numbers (in nanoseconds) to be negative, then MMCM2 is advancing (rather than delaying) sysClk on the way to becoming CLKOUT3.  The MMCM clock module can advance a clock by phase-shifting the clock.  We often use this capability of the MMCM for FPGA IO where the IO-clock needs to be advanced with-respect-to the IO-data in order to place the clock capture-edge in the middle of the data-eye.

The reason that these numbers are different (even though it is the same MMCM) is because timing analysis knows that delay/advance of the MMCM is variable.  So, it uses a number that is a little low for part of the analysis and a number that is little high for another part of the analysis - so that the overall timing analysis is a worse-case analysis.

Mark

2 Replies
219 Views
Registered: ‎01-22-2015

Re: TIming analysis of the input delay.

Jump to solution

@lis_user1 

     What do the MMCM2_ADV prop_mmcme2_adv_CLKIN1_CLKOUT3 of 6.087 and 5.343 refer to here?
Since the timing report is showing these numbers (in nanoseconds) to be negative, then MMCM2 is advancing (rather than delaying) sysClk on the way to becoming CLKOUT3.  The MMCM clock module can advance a clock by phase-shifting the clock.  We often use this capability of the MMCM for FPGA IO where the IO-clock needs to be advanced with-respect-to the IO-data in order to place the clock capture-edge in the middle of the data-eye.

The reason that these numbers are different (even though it is the same MMCM) is because timing analysis knows that delay/advance of the MMCM is variable.  So, it uses a number that is a little low for part of the analysis and a number that is little high for another part of the analysis - so that the overall timing analysis is a worse-case analysis.

Mark

Highlighted
Explorer
Explorer
127 Views
Registered: ‎11-17-2015

Re: TIming analysis of the input delay.

Jump to solution

Thank you markg.

 

0 Kudos