08-19-2020 07:55 AM
We have a design running PCIe Gen 2 x4 (Artix-7, XC7A35T-2CSG325), that has intermittent PCIe packet (TLP) drops. The drops are random for every large DMA transfer.
I have an impression that these drops are related to the bitfile that has a TPWS violation on the PIPECLK. Once in several iterations we do get a clean bitfile with no TPWS violations, and it seems (not 100% sure) that such bitfile does not drop TLPs.
We generate the PCIe Endpoint using VIVADO 2018.3, without any manual intervention or changes etc. We are using it in 64-bit mode (250 MHz) and are working on 128-bit support to drop the clock rate.
Can Xilinx please comment on this? Is this really the limit? The FPGA usage is about 30% slices. I attach the screenshot for illustration.
03-24-2021 02:53 AM
TPWS (pulse width violations) has two types of violations generally those are minimum pulse width and max skew.
In above post I can see max skew issue. TPWS are silicon level requirements and those cannot be solved using exception constraints and cannot be ignored for expected hardware results.
Max skew violations states that the skew requirement for coreclk and pipeclk is beyond expectation. The required skew or maximum allowed skew between two clock is 0.410ns but in your design is is 0.511 hence -0.101ns as slack.
Need to manage clocking topology, clock placement etc in order to fix these violations. Ultimately you need to reduce the relative skew between two clocks in the range of requirement to get it fixed.