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bell_a
Visitor
Visitor
1,321 Views
Registered: ‎01-30-2018

The design does not meet the requirements of the time

Hey. When implementing the project, the warning is changed. The implementation ends with the message:

[Timing 38-282] The design does not meet the requirements of the time. For detailed information about time delinquencies, see Consolidated Statement of Dates.

The implementation was launched using the Flow_RunPhysOpt strategy and the AgressiveFanoutOpt directive (as suggested in this post https://forums.xilinx.com/t5/Implementation/Timing-38-282- The-design-failed-to-meet-the-timing-requirements / pl. 674801 # M14398).

I do not know what can be done to correct this problem. Please help me.

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4 Replies
thakurr
Moderator
Moderator
1,307 Views
Registered: ‎09-15-2016

Hi @bell_a

 

From the shared report, I checked the most violated path with slack setup slack -6.795 ns and with this much less requirement of 0.032 ns, it is impossible for tool to meet the setup. You need to check your max delay constraints here to meet the timing requirement.

 

Regards

Rohit

Regards
Rohit
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bell_a
Visitor
Visitor
1,293 Views
Registered: ‎01-30-2018

@thakurr

Tell me, please, where exactly should I look? In an xdc file? Could you tell me what to look for here?

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watari
Teacher
Teacher
1,273 Views
Registered: ‎06-16-2013

Hi @bell_a

 

Would you make sure worst negative slack path at line 27324 on report file ?

In this part, tool can not meet your criteria. Because of it is different clock domain.

 

I suggest to clear your criteria between CLK_125M_P and VIRTUAL_clk2xadc_c.

 

Also, as @thakurr already mentioned before, if your criteria is correct, I suggest to use "set_max_delay" and "set_min_delay" commands instead of "VIRTUAL_clk2xadc_c" clock setting.

 

Best regards,

thakurr
Moderator
Moderator
1,254 Views
Registered: ‎09-15-2016

Hi @bell_a

 

First of all make sure whether this 6.14 MHz (162.784 ns) virtual_clk2xadc_c clock can meet the design criteria or not. If yes, you need to write set_max_delay and set_min_delay constraint to define relationship between these unrelated asynchronous clock domains (CLK_125M_P and virtual_clk2xadc_c) and other unrelated asynchronous clocks domain.

You can use set_max_delay -datapath_only option if paths doesn't have min delay requirement. This will also ignore skew computation from slack calculation. Refer UG903 for more details.

 

Regards

Rohit

Regards
Rohit
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