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Abady
Contributor
Contributor
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Registered: ‎08-11-2020

The effect of timing violations

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I made an IP that convert AXIS video into BT656 video in order to contact a DAC that generates analog video.

 

The IP works and I tried it multiple times. The problem is that after sometimes when I modify the HARDWARE design and generate new bitstream it doesn't work, even though data feed correctly to the IP ( I check some random samples using System ILA).

I used to make random changes and it work sometimes and others it doesn't, but I need to figure out the reason for this problem, so I started looking out for the reason, I found timing violation in WNS(-4.758) and TNS(-1426.577), could these violations cause such problem? and if yes how to deal with them?

 

I have zero experience in dealing with timing issue.

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dpaul24
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Registered: ‎08-07-2014

@Abady ,

A design which fails timing is as good as a non working design. Begin here...

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0006-vivado-design-analysis-and-timing-closure-hub.html

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dpaul24
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Registered: ‎08-07-2014

@Abady ,

A design which fails timing is as good as a non working design. Begin here...

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0006-vivado-design-analysis-and-timing-closure-hub.html

------------FPGA enthusiast------------
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dsheils
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Registered: ‎01-05-2017

Hi @Abady 

Ideally you should be following our UFDM (Ultrafast Design Methodology) to ensure good design practices such as pristine constraints, analysis etc.

Refer to UG1292 which is a quick reference guide for timing closure.

You should be checking that your design passes timing after each of the stages: synth_design, place_design and route_design. This is explained more in UG1292.

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drjohnsmith
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Registered: ‎07-09-2009

Any design , that works on a random sample of one hardware,

    is not IMHO ready to ship,

If you have a timing violation, and you are constrained correctly ,

  then you need to sort out your timing problems

 

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Abady
Contributor
Contributor
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Registered: ‎08-11-2020

Thank you @dpaul24  for these set of references, I will check them.

 

UG1292 seems to be good place to start, thank you @dsheils 

@drjohnsmithI agree with you, the problem is a simple change in the design break the timing violation, this is hard to manage.

 

mvisser
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455 Views
Registered: ‎11-06-2018

Thanks for this question, the links here are excellent references.

A design that doesn't make timing sometimes works under the right conditions, however this is typically where issues like "the board heats up and then stops working" or "it seems to work for lower input frequencies than the timing constraints were set up for" comes up. We have a systems engineer who is of the opinion that we should just cool down all FPGAs as a standard practise because we've seen the "issues when the board heats up" multiple times with COTS boards, and this is preventable. 100% agree with the statement in the accepted solution - if we can all learn to not ship unless the design meets timing, then we prevent problems for our customers later.

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