The full list of clock modifying blocks

[jingli-fidus]

in UG903 Page 59, it gives some examples of Clock Modifying Blocks, like:

MMCM, PLL, BUFR. 

Fo the clock modfiying blocks, my understanding is this block will make  the input clock and output clock different. We need to manually define a generated clock, or it is auto-generated by Vivado.

But what are the full list of clock modifying blocks? Whether I need to define the generated clock after BUFH, BUFG?

Hope someone can help or show related reference.

Thanks in advance.

[venkata]

For the clock modifying blocks, you could set the constraint on input clock. It will get propagated to the output clocks.

There seems to be an exception for GT blocks which can also be considered as clock modifying blocks. For GTs, you need to constrain both input and output clocks.

[smarell]

Hi,

For Clock Management Tiles (PLL/MMCM) you just need to create a clock constraint on the input clock nets. The tool auto-propagates the constraints to output clocks.

If it is a buffer, then you can just write a constraint on the output of the buffer.

Regards,
Krishna

[jingli-fidus]

So that means, even for BUFG, Vivado thinks the input and output clocks are different clocks? This criteria works for all the clock buffers?

So can I conclude the Clock Management Tiles includes MMCM, PLL, and all clock buffers (BUFG, BUFR, BUFH)?

Thanks.

[vsrunga]

Hi,

I think yes, please refer respective device Clocking resources User Guide for more details, UG472 for 7-series, Chapter-3 I guess.

Hope this helps.

Regards,

Vanitha.

[avrumw · Accepted solution]

Clock buffers (in general) are not clock modifying blocks. The clock that is applied to the input pin propagates through the clock buffer, but it is still the same clock. So, no, BUFGs and BUFIOs and BUFHs are not clock modifying blocks.

Clock modifying blocks are blocks that change the attributes of the clock, either in terms of frequency or phase (or both). It is important to note, though, that phase and propagation are different concepts in Vivado; a clock that is 90 degrees phase shifted (i.e. from an MMCM) is different than a clock that is delayed by 1/4 of a clock period (i.e. from an IDELAY). The difference is subtle, but extremely important.

So, the complete list of clock modifying blocks are the MMCM, PLL and BUFR. The BUFR is only a clock modifying block since it can change the frequency by doing integer division of the frequency; that's why the BUFR is a clock modifying block, but the BUFG isn't. The GTP/GTX/GTH/GTZ should be clock modifying blocks, since the clocks on RXCLKOUT* and TXCLKOUT* are related to, but not identical to, the reference clock. However, at the moment (at least as of the early 2013 versions, I haven't checked 2013.3), the automatic derivation of the clocks on these outputs is not done.

For the others (MMCM, PLL, BUFR), as others have said, if you attach a clock to the input pin, when the clock propagates to the clock modifying block, the tool will automatically generate new clocks on the outputs of the block. These clocks will be generated clocks, as if they were created with the create_generated_clock command.

Other blocks can modify the clock - like a BUFHCE or BUFGCE, but that has more to do with how the CE is managed. In some cases, the designer may want to generate a new generated clock on the output of the BUFHCE/BUFGCE using the "create_generated_clock" command.

Avrum

[jingli-fidus]

Thanks very much, Avrum.

So the Vivado can also automatically generate the clock from BUFR ? Before this I thought Vivado only auto generate clocks for output of MMCM and PLL. So that means Vivado can auto generate the clock for all CMBs except GT.

What do you mean "CE" in "but that has more to do with how the CE is managed."?

Thanks.

[avrumw]

If you use a BUFHCE or BUFGCE where the CE is always asserted one out of every N clock periods, then the resulting output signal behaves like a clock, and can be defined as such.

For example, if the CE input of the BUFGCE is asserted one out of every 3 clocks, it behaves like a clock with 1/3 of the frequency of the original clock. This can be defined in Vivado as

create_generated_clock -name divided_clock -source [get_pins bufgce_inst/I] -divide_by 3 [get_pins bufgce_inst/O]

Avrum