Hi! I get clocks using 2 casceded PLLs (1ts - 65Mhz, 2nd -100Mhz).
I use fifo to transfer data from one clock domain to another. I have constraint with PERIOD parameters for both clocks. After timing analysys I got: Slack (setup path): -4.847ns. How can I solve this problem? If I clock all design with the same clock (100 or 65) I have no timing issues, but I have to transfer data with this different rates.