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Contributor
Contributor
575 Views
Registered: ‎09-22-2019

[Timing 38-282] The design failed to meet the timing requirements. setup violation

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This is my first time to ask a question here. Maybe im not good at describing my problem. 

I got a problem of setup violation. Actually I just created one IP called my_ip  that contain  two inputs and two outputs. The two of inputs are  totally independent , and they have one output respectively. 

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the picture below is the problem i got

f1.PNG

 

 

 

 

 

 

 

 

gggg.PNG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Is there anyone know how to fix this problem?  should I  add someting like set_input_delay to this constraint to make the setup slack better?

I really need your help!! thank you!

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Guide avrumw
Guide
522 Views
Registered: ‎01-23-2009

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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Looking at the timing report, this is a "normal synchronous path" - the start and end flip-flop are on the same clock domain, and the requirement on the path is 20ns (so driven by a 50MHz clock). So this is not a clock domain crossing path...

The problem with this path is it is just too long - there is WAY too much combinatorial logic on the path - from the timing report there are 46 levels of logic, of which 33 are LUTs and the rest are MUXes; MUXes can be more or less free if they are tightly bound with the LUT - I can't tell from this report. So you have somewhere between 33 and 46 routes from LUT to LUT - there is no way the FPGA can do this in 20ns.

Furthermore, your startpoint and endpoint are both in the AXI infrastructure - presumably they go through your IP block. This implies that your IP block is purely combinatorial (there are no flip-flops on this path). This is bad from a number of reasons:

  • There is an inherent limit on the complexity of logic you can do purely combinatorially and
  • It is certainly not recommended (and maybe not even legal from a protocol point of view) to have a purely combinatorial AXI endpoint

So whatever you are trying to do, you need to architect so that it is properly pipelined. Even if you plan to only operate on one piece of data at a time (so you are not trying to overlap multiple operations), then you still need to put flip-flops in your computational path to allow it to operate at the AXI speed.

Avrum

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9 Replies
564 Views
Registered: ‎09-17-2018

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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Vivado assumes all clock crossings are constrained,

When you ger a realling big negative slack, it is usually because you have failed to have a timing ignore constraint.  The tool is trying to meet timing for a clockto clock path that it should not be trying to constrain.

l.e.o.

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Contributor
Contributor
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Registered: ‎09-22-2019

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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Thanks for your reply!

so do you mean i dont need to add any timing constraints on it?

could you give me some examples of how to fix this ? 


Thank you!

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540 Views
Registered: ‎09-17-2018

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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Highlighted
Guide avrumw
Guide
523 Views
Registered: ‎01-23-2009

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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Looking at the timing report, this is a "normal synchronous path" - the start and end flip-flop are on the same clock domain, and the requirement on the path is 20ns (so driven by a 50MHz clock). So this is not a clock domain crossing path...

The problem with this path is it is just too long - there is WAY too much combinatorial logic on the path - from the timing report there are 46 levels of logic, of which 33 are LUTs and the rest are MUXes; MUXes can be more or less free if they are tightly bound with the LUT - I can't tell from this report. So you have somewhere between 33 and 46 routes from LUT to LUT - there is no way the FPGA can do this in 20ns.

Furthermore, your startpoint and endpoint are both in the AXI infrastructure - presumably they go through your IP block. This implies that your IP block is purely combinatorial (there are no flip-flops on this path). This is bad from a number of reasons:

  • There is an inherent limit on the complexity of logic you can do purely combinatorially and
  • It is certainly not recommended (and maybe not even legal from a protocol point of view) to have a purely combinatorial AXI endpoint

So whatever you are trying to do, you need to architect so that it is properly pipelined. Even if you plan to only operate on one piece of data at a time (so you are not trying to overlap multiple operations), then you still need to put flip-flops in your computational path to allow it to operate at the AXI speed.

Avrum

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Contributor
Contributor
408 Views
Registered: ‎09-22-2019

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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thanks for your reply

so should I change my architecture first right?
should I add any constraint on this xdc?  

ss.PNG

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Registered: ‎06-21-2017

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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You may not need to change your constraints on this path.  You need to add registers on this path inside yur IP.  This will help break up the 46 levels of logic into smaller paths that can complete in 20 nS. 

Contributor
Contributor
271 Views
Registered: ‎09-22-2019

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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thank you , I will try to do that .

By the way . if I still use the bitstream under the situation that I didnt fix the timing violation  ,  the error will occur on sdk?

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Guide avrumw
Guide
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Registered: ‎01-23-2009

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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You won't get any error from the SDK process itself, but if you try and then download this to a board, you shouldn't expect your IP to work; the data that comes back from the IP will either be wrong, partially right, or any combination of the two - it will depend on the actual board you run it on (and the temperature).

In general, you should not expect a design with timing violations (particularly if they are "significant" violations - and yours are very significant - almost 100% of the clock period) to work.

Avrum

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Contributor
Contributor
230 Views
Registered: ‎09-22-2019

Re: [Timing 38-282] The design failed to meet the timing requirements. setup violation

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do you think it will take long time here?

im trying to use pipleline to make the setup time lower..

d.PNG

 

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